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This commit is contained in:
Andrei Solodovnikov
2024-02-21 11:48:18 +03:00
parent a01446eb43
commit 3dcb0b76f9
67 changed files with 686 additions and 251 deletions
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10
Labs/01. Adder/board files/nexys_adder.sv
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@@ -1,3 +1,13 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Nikita Bulavin
* Email(s) : nekkit6@edu.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module nexys_adder(
input CLK100,
input resetn,

17
Labs/01. Adder/tb_fulladder.sv
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@@ -1,12 +1,13 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Andrei Solodovnikov
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
// Module Name: tb_fulladder
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Description: tb for 1-bit fulladder
//////////////////////////////////////////////////////////////////////////////////
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module tb_fulladder();

17
Labs/01. Adder/tb_fulladder32.sv
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@@ -1,12 +1,13 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Andrei Solodovnikov
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
// Module Name: tb_fulladder32
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Description: tb for 32-bit fulladder
//////////////////////////////////////////////////////////////////////////////////
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module tb_fulladder32();

17
Labs/01. Adder/tb_fulladder4.sv
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@@ -1,12 +1,13 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Andrei Solodovnikov
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
// Module Name: tb_fulladder4
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Description: tb for 4-bit fulladder
//////////////////////////////////////////////////////////////////////////////////
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module tb_fulladder4();

10
Labs/02. Arithmetic-logic unit/alu_opcodes_pkg.sv
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@@ -1,3 +1,13 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
package alu_opcodes_pkg;
localparam ALU_OP_WIDTH = 5;

4
Labs/02. Arithmetic-logic unit/board files/nexys_alu.sv
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@@ -1,15 +1,13 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* File : nexys_alu.sv
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Alexander Kharlamov
* Email(s) : sasha_xarlamov@org.miet.ru
See LICENSE file for licensing details.
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module nexys_alu(
input logic clk_i,
input logic arstn_i,

18
Labs/02. Arithmetic-logic unit/tb_alu.sv
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@@ -1,13 +1,13 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Nikita Bulavin
// Module Name: tb_miriscv_alu
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Description: tb for miriscv alu
//////////////////////////////////////////////////////////////////////////////////
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Nikita Bulavin
* Email(s) : nekkit6@edu.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module tb_miriscv_alu();
import alu_opcodes_pkg::*;

34
Labs/03. Register file and memory/board files/nexys_rf_riscv.sv
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@@ -1,14 +1,24 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Nikita Bulavin
* Email(s) : nekkit6@edu.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module nexys_rf_riscv(
input CLK100,
input resetn,
input BTND, BTNU, BTNL, BTNR, BTNC,
input BTND, BTNU, BTNL, BTNR, BTNC,
input [15:0] SW,
output [15:0] LED,
output CA, CB, CC, CD, CE, CF, CG, DP,
output [7:0] AN,
output LED16_B, LED16_G, LED16_R, LED17_B, LED17_G, LED17_R
);
wire [31:0] WD3;
wire WE;
wire [31:0] RD1;
@@ -75,40 +85,40 @@ always @(posedge CLK100) begin
a1 <= BTNL? SW[4:0]: a1;
a2 <= BTNC? SW[4:0]: a2;
a3 <= BTNR? SW[4:0]: a3;
rd1 <= BTNU? RD1: rd1;
rd2 <= BTNU? RD2: rd2;
case (1'b0)
ANreg[0]: begin
ANreg[0]: begin
semseg <= (rd2) % 5'h10;
//DPr <= 1'b1;
end
ANreg[1]: begin
ANreg[1]: begin
semseg <= (rd2 / 'h10) % 5'h10;
//DPr <= 1'b1;
end
ANreg[2]: begin
ANreg[2]: begin
semseg <= (rd2 / 'h100) % 5'h10;
//DPr <= 1'b1;
end
ANreg[3]: begin
ANreg[3]: begin
semseg <= (rd2 / 'h1000) % 5'h10;
//DPr <= 1'b1;
end
ANreg[4]: begin
ANreg[4]: begin
semseg <= (rd1) % 5'h10;
//DPr <= 1'b1;
end
ANreg[5]: begin
ANreg[5]: begin
semseg <= (rd1 / 'h10) % 5'h10;
//DPr <= 1'b1;
end
ANreg[6]: begin
ANreg[6]: begin
semseg <= (rd1 / 'h100) % 5'h10;
//DPr <= 1'b1;
end
ANreg[7]: begin
ANreg[7]: begin
semseg <= (rd1 / 'h1000) % 5'h10;
//DPr <= 1'b1;
end

18
Labs/03. Register file and memory/tb_data_mem.sv
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@@ -1,13 +1,13 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Nikita Bulavin
// Module Name: tb_data_mem
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Description: tb for data memory
//////////////////////////////////////////////////////////////////////////////////
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Nikita Bulavin
* Email(s) : nekkit6@edu.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module tb_data_mem();
parameter ADDR_SIZE = 16384;

18
Labs/03. Register file and memory/tb_instr_mem.sv
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@@ -1,13 +1,13 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Nikita Bulavin
// Module Name: tb_instr_mem
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Description: tb for instruction memory
//////////////////////////////////////////////////////////////////////////////////
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Nikita Bulavin
* Email(s) : nekkit6@edu.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module tb_instr_mem();
parameter ADDR_SIZE = 4096;

18
Labs/03. Register file and memory/tb_rf_riscv.sv
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@@ -1,13 +1,13 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Nikita Bulavin
// Module Name: tb_rf_riscv
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Description: tb for RISC-V register file
//////////////////////////////////////////////////////////////////////////////////
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Nikita Bulavin
* Email(s) : nekkit6@edu.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module tb_rf_riscv();
logic CLK;

14
Labs/04. Primitive programmable device/board files/nexys_cybercobra.sv
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@@ -1,12 +1,22 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Nikita Bulavin
* Email(s) : nekkit6@edu.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module nexys_CYBERcobra_dz(
input CLK100,
input resetn,
input BTND,
input [15:0] SW,
output CA, CB, CC, CD, CE, CF, CG,
output CA, CB, CC, CD, CE, CF, CG,
output [7:0] AN
);
CYBERcobra dut(
.clk_i(btn),
.rst_i(!resetn),

14
Labs/04. Primitive programmable device/board files/nexys_cybercobra_demo.sv
View File

@@ -1,12 +1,22 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Nikita Bulavin
* Email(s) : nekkit6@edu.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module nexys_CYBERcobra(
input CLK100,
input resetn,
input BTND,
input [15:0] SW,
output CA, CB, CC, CD, CE, CF, CG,
output CA, CB, CC, CD, CE, CF, CG,
output [7:0] AN
);
CYBERcobra dut(
.clk_i(CLK100),
.rst_i(!resetn),

28
Labs/04. Primitive programmable device/tb_cybercobra.sv
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@@ -1,22 +1,22 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Nikita Bulavin
// Module Name: tb_cybercobra
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Description: tb for CYBERcobra 3000 Pro 2.1
//////////////////////////////////////////////////////////////////////////////////
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Nikita Bulavin
* Email(s) : nekkit6@edu.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module tb_CYBERcobra();
CYBERcobra dut(
.clk_i(clk),
.rst_i(rstn),
.sw_i (sw_i ),
.out_o(OUT)
);
wire [31:0] OUT;
reg clk;
reg rstn;
@@ -24,8 +24,8 @@ module tb_CYBERcobra();
initial clk <= 0;
always #5 clk = ~clk;
initial begin
initial begin
$display( "\nStart test: \n\n===============================================\nAdd CYBERcobra signals to the waveform and then\nCLICK THE BUTTON 'Run All'\n===============================================\n"); $stop();
rstn = 1'b1;
#10;
@@ -37,5 +37,5 @@ module tb_CYBERcobra();
$display("\n The test is over \n See the internal signals of the CYBERcobra on the waveform \n");
$finish;
end
endmodule

10
Labs/05. Main decoder/alu_opcodes_pkg.sv
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@@ -1,3 +1,13 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
package alu_opcodes_pkg;
localparam ALU_OP_WIDTH = 5;

10
Labs/05. Main decoder/csr_pkg.sv
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@@ -1,3 +1,13 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
package csr_pkg;
localparam CSR_RW = 3'b001;

10
Labs/05. Main decoder/riscv_pkg.sv
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@@ -1,3 +1,13 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
package riscv_pkg;
import alu_opcodes_pkg::*;

19
Labs/05. Main decoder/tb_decoder_riscv.sv
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@@ -1,14 +1,13 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Nikita Bulavin
// Module Name: tb_decoder_riscv
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Description: tb for decoder riscv
//////////////////////////////////////////////////////////////////////////////////
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Nikita Bulavin
* Email(s) : nekkit6@edu.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module tb_decoder_riscv();
import riscv_pkg::*;

10
Labs/06. Datapath/alu_opcodes_pkg.sv
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@@ -1,3 +1,13 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
package alu_opcodes_pkg;
localparam ALU_OP_WIDTH = 5;

18
Labs/06. Datapath/board files/nexys_riscv_unit.sv
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@@ -1,11 +1,21 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Nikita Bulavin
* Email(s) : nekkit6@edu.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module nexys_riscv_unit(
input CLK100,
input resetn,
input BTND,
output CA, CB, CC, CD, CE, CF, CG,
output CA, CB, CC, CD, CE, CF, CG,
output [7:0] AN
);
riscv_unit unit(
.clk_i(btn),
.rst_i(!resetn)
@@ -14,7 +24,7 @@ module nexys_riscv_unit(
wire [31:0] instr_addr;
wire [31:0] instr;
reg btn;
assign instr_addr = unit.core.instr_addr_o;
assign instr = unit.core.instr_i;
@@ -140,7 +150,7 @@ module nexys_riscv_unit(
endcase
end
end
end
endmodule

12
Labs/06. Datapath/csr_pkg.sv
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@@ -1,3 +1,13 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
package csr_pkg;
localparam CSR_RW = 3'b001;
@@ -6,7 +16,7 @@ package csr_pkg;
localparam CSR_RWI = 3'b101;
localparam CSR_RSI = 3'b110;
localparam CSR_RCI = 3'b111;
localparam MIE_ADDR = 12'h304;
localparam MTVEC_ADDR = 12'h305;
localparam MSCRATCH_ADDR = 12'h340;

10
Labs/06. Datapath/riscv_pkg.sv
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@@ -1,3 +1,13 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
package riscv_pkg;
import alu_opcodes_pkg::*;

18
Labs/06. Datapath/tb_riscv_unit.sv
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@@ -1,13 +1,13 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Nikita Bulavin
// Module Name: tb_riscv_unit
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Description: tb for datapath
//////////////////////////////////////////////////////////////////////////////////
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Nikita Bulavin
* Email(s) : nekkit6@edu.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module tb_riscv_unit();
reg clk;

18
Labs/08. Load-store unit/tb_lsu.sv
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@@ -1,13 +1,13 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Andrei Solodovnikov
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
// Module Name: lsu_testbench
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Description: tb for Load&Store module
//
//////////////////////////////////////////////////////////////////////////////////
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module tb_lsu();
import riscv_pkg::*;
logic clk_i ;

12
Labs/10. Interrupt subsystem/csr_pkg.sv
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@@ -1,3 +1,13 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
package csr_pkg;
localparam CSR_RW = 3'b001;
@@ -6,7 +16,7 @@ package csr_pkg;
localparam CSR_RWI = 3'b101;
localparam CSR_RSI = 3'b110;
localparam CSR_RCI = 3'b111;
localparam MIE_ADDR = 12'h304;
localparam MTVEC_ADDR = 12'h305;
localparam MSCRATCH_ADDR = 12'h340;

18
Labs/10. Interrupt subsystem/tb_csr.sv
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@@ -1,13 +1,13 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Daniil Strelkov
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Daniil Strelkov
* Email(s) : @edu.miet.ru
// Module Name: tb_csr
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Description: tb for CSR controller
//
//////////////////////////////////////////////////////////////////////////////////
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module tb_csr();
logic clk_i;

19
Labs/10. Interrupt subsystem/tb_irq.sv
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@@ -1,14 +1,13 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Daniil Strelkov
// Module Name: tb_irq
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Description: tb for interrupt controller
//
//////////////////////////////////////////////////////////////////////////////////
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Daniil Strelkov
* Email(s) : @edu.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module tb_irq();
logic clk_i;
logic rst_i;

19
Labs/11. Interrupt integration/tb_irq_unit.sv
View File

@@ -1,14 +1,13 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Andrei Solodovnikov
// Module Name: tb_riscv_unit
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Description: tb for riscv unit with irq support
//////////////////////////////////////////////////////////////////////////////////
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module tb_irq_unit();
reg clk;

19
Labs/12. Daisy chain/tb_daisy_chain.sv
View File

@@ -1,14 +1,13 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Solodovnikov Andrei
// Module Name: tb_daisy_chain
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Description: tb for daisy chain
//
//////////////////////////////////////////////////////////////////////////////////
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module tb_daisy_chain();
logic clk_i, rst_i, ready_i, irq_ret_i;

10
Labs/13. Peripheral units/firmware/software/ps2_hex.S
View File

@@ -1,3 +1,13 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
_start:
# Инициализируем начальные значения регистров
0: 030000b7 li x1 , 0x03000000 # сохраняем базовый адрес клавиатуры

10
Labs/13. Peripheral units/firmware/software/ps2_vga.S
View File

@@ -1,3 +1,13 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
_start:
# Инициализируем начальные значения регистров
0: 030000b7 li x1, 0x03000000 # сохраняем базовый адрес клавиатуры

10
Labs/13. Peripheral units/firmware/software/rx_hex.S
View File

@@ -1,3 +1,13 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
_start:
# Инициализируем начальные значения регистров
0: 050000b7 li x1 , 0x05000000 # сохраняем базовый адрес uart_rx

10
Labs/13. Peripheral units/firmware/software/rx_led.S
View File

@@ -1,3 +1,13 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
_start:
# Инициализируем начальные значения регистров
0: 050000b7 li x1, 0x05000000 # сохраняем базовый адрес uart_rx

10
Labs/13. Peripheral units/firmware/software/rx_tx.S
View File

@@ -1,3 +1,13 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
_start:
# Инициализируем начальные значения регистров
0: 050000b7 li x1 , 0x05000000 # сохраняем базовый адрес uart_rx

10
Labs/13. Peripheral units/firmware/software/sw_led.S
View File

@@ -1,3 +1,13 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
_start:
# Инициализируем начальные значения регистров
0: 010000b7 li x1, 0x01000000 # сохраняем базовый адрес переключателей

23
Labs/13. Peripheral units/peripheral modules/PS2Receiver.sv
View File

@@ -1,3 +1,26 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: Digilent Inc.
// Engineer: Thomas Kappenman
//
// Create Date: 03/03/2015 09:33:36 PM
// Design Name:
// Module Name: PS2Receiver
// Project Name: Nexys4DDR Keyboard Demo
// Target Devices: Nexys4DDR
// Tool Versions:
// Description: PS2 Receiver module used to shift in keycodes from a keyboard plugged into the PS2 port
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// Modified in 2023 by engineers of
// National Research University of Electronic Technology
// Nikita Bulavin and Andrei Solodovnikov
//
//////////////////////////////////////////////////////////////////////////////////
module PS2Receiver(
input logic clk_i,
input logic rst_i,

10
Labs/13. Peripheral units/peripheral modules/hex_digits.sv
View File

@@ -1,3 +1,13 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Nikita Bulavin
* Email(s) : nekkit6@edu.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module hex_digits(
input logic clk_i,
input logic rst_i,

10
Labs/13. Peripheral units/peripheral modules/uart_rx.sv
View File

@@ -8,6 +8,16 @@
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
// This file has been taken from https://github.com/pulp-platform/apb_uart_sv
// and modified by Andrei Solodovnikov in order to be used in
// Architectures of Processor Systems (APS) lab work project
// Changelog:
// some of the input signals has been hardcoded to constant values
// cfg_div_i input has been replaced by baudrate_i input signal.
// The signal cfg_div_i is now controled by baudrate_i input, and this control
// logic is work from assumption that clk_i is 10 MHz.
module uart_rx (
input logic clk_i,
input logic rst_i,

10
Labs/13. Peripheral units/peripheral modules/uart_tx.sv
View File

@@ -8,6 +8,16 @@
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
// This file has been taken from https://github.com/pulp-platform/apb_uart_sv
// and modified by Andrei Solodovnikov in order to be used in
// Architectures of Processor Systems (APS) lab work project
// Changelog:
// some of the input signals has been hardcoded to constant values
// cfg_div_i input has been replaced by baudrate_i input signal.
// The signal cfg_div_i is now controled by baudrate_i input, and this control
// logic is work from assumption that clk_i is 10 MHz.
module uart_tx (
input logic clk_i,
input logic rst_i,

10
Labs/13. Peripheral units/peripheral modules/vgachargen.sv
View File

@@ -1,3 +1,13 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Alexander Kharlamov
* Email(s) : sasha_xarlamov@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module vgachargen
import vgachargen_pkg::*;
#(

10
Labs/13. Peripheral units/peripheral modules/vgachargen_pkg.sv
View File

@@ -1,3 +1,13 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Alexander Kharlamov
* Email(s) : sasha_xarlamov@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
package vgachargen_pkg;
parameter int unsigned HD = 640; // Display area

10
Labs/13. Peripheral units/sys_clk_rst_gen.sv
View File

@@ -1,3 +1,13 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module sys_clk_rst_gen#(
parameter DIV_WIDTH = 4
)(

19
Labs/13. Peripheral units/tb_riscv_unit.sv
View File

@@ -1,14 +1,13 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Andrei Solodovnikov
// Module Name: tb_riscv_unit
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Description: tb for peripheral units
//
//////////////////////////////////////////////////////////////////////////////////
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module tb_riscv_unit();
logic clk;

10
Labs/14. Programming/linker_script.ld
View File

@@ -1,3 +1,13 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
OUTPUT_FORMAT("elf32-littleriscv") /* Указываем порядок следования байт */
ENTRY(_start) /* мы сообщаем компоновщику, что первая

10
Labs/14. Programming/platform.h
View File

@@ -1,3 +1,13 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
#pragma once
#include <stdint.h>

10
Labs/14. Programming/startup.S
View File

@@ -1,3 +1,13 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
.section .boot
.global _start

10
Labs/15. Programming device/flash.py
View File

@@ -1,3 +1,13 @@
# -----------------------------------------------------------------------------
# Project Name : Architectures of Processor Systems (APS) lab work
# Organization : National Research University of Electronic Technology (MIET)
# Department : Institute of Microdevices and Control Systems
# Author(s) : Andrei Solodovnikov
# Email(s) : hepoh@org.miet.ru
#
# See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
# ------------------------------------------------------------------------------
#
import argparse
import serial

19
Labs/15. Programming device/tb_bluster.sv
View File

@@ -1,14 +1,13 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Solodovnikov Andrei
// Module Name: tb_blaster
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Description: tb for programming device
//
//////////////////////////////////////////////////////////////////////////////////
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module tb_blaster();
logic clk_i;

19
Labs/15. Programming device/tb_top_asic.sv
View File

@@ -1,14 +1,13 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Solodovnikov Andrei
// Module Name: tb_top_asic
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Description: tb for top level entity
//
//////////////////////////////////////////////////////////////////////////////////
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module tb_top_asic();
logic clk10mhz_i;

10
Labs/16. Coremark/Makefile
View File

@@ -1,3 +1,13 @@
# -----------------------------------------------------------------------------
# Project Name : Architectures of Processor Systems (APS) lab work
# Organization : National Research University of Electronic Technology (MIET)
# Department : Institute of Microdevices and Control Systems
# Author(s) : Andrei Solodovnikov
# Email(s) : hepoh@org.miet.ru
#
# See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
# ------------------------------------------------------------------------------
#
CC_PATH = /c/riscv_cc/bin
CC_PREFIX = riscv-none-elf

10
Labs/16. Coremark/linker_script.ld
View File

@@ -1,3 +1,13 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
OUTPUT_FORMAT("elf32-littleriscv") /* Указываем порядок следования байт */
ENTRY(_start) /* мы сообщаем компоновщику, что первая

10
Labs/16. Coremark/startup.S
View File

@@ -1,3 +1,13 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
.section .boot
.global _start

19
Labs/16. Coremark/tb_coremark.sv
View File

@@ -1,14 +1,13 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Solodovnikov Andrei
// Module Name: tb_coremark
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Description: tb for running Coremark
//
//////////////////////////////////////////////////////////////////////////////////
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module tb_coremark();
logic clk10mhz_i;

19
Labs/16. Coremark/tb_timer.sv
View File

@@ -1,14 +1,13 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Solodovnikov Andrei
// Module Name: tb_timer
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Description: tb for timer
//
//////////////////////////////////////////////////////////////////////////////////
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module tb_timer();
logic clk_i;

10
Labs/Made-up modules/lab_01.fulladder32.sv
View File

@@ -1,3 +1,13 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module fulladder32(
input logic [31:0] a_i,
input logic [31:0] b_i,

10
Labs/Made-up modules/lab_03.data_mem.sv
View File

@@ -1,3 +1,13 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Nikita Bulavin
* Email(s) : nekkit6@edu.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module data_mem (
input logic clk_i,
input logic [31:0] addr_i,

10
Labs/Made-up modules/lab_03.instr_mem.sv
View File

@@ -1,3 +1,13 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Nikita Bulavin
* Email(s) : nekkit6@edu.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module instr_mem(
input logic [31:0] addr_i,
output logic [31:0] read_data_o

10
Labs/Made-up modules/lab_03.register_file.sv
View File

@@ -1,3 +1,13 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Nikita Bulavin
* Email(s) : nekkit6@edu.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module rf_riscv(
input logic clk_i,
input logic write_enable_i,

18
Labs/Made-up modules/lab_05.decoder.sv
View File

@@ -1,13 +1,13 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Alexey Kozin
// Module Name: decoder_riscv
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Description: main decoder for risc-v processor
//////////////////////////////////////////////////////////////////////////////////
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Alexey Kozin
* Email(s) : @edu.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module gpr_we_table (gis_ew_rpg, edocpo_6, edocpo_5, edocpo_4, edocpo_3, edocpo_2);
output logic gis_ew_rpg;
input edocpo_6, edocpo_5, edocpo_4, edocpo_3, edocpo_2;

18
Labs/Made-up modules/lab_07.ext_mem.sv
View File

@@ -1,13 +1,13 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Andrei Solodovnikov
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
// Module Name: ext_mem
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Description: external memory with byte_enable support
//
//////////////////////////////////////////////////////////////////////////////////
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module ext_mem(
input logic clk_i,
input logic mem_req_i,

18
Labs/Made-up modules/lab_08.lsu.sv
View File

@@ -1,13 +1,13 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Andrei Solodovnikov
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
// Module Name: lsu_testbench
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Description: Load&Store Unit
//
//////////////////////////////////////////////////////////////////////////////////
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module riscv_lsu(
input logic clk_i,
input logic rst_i,

26
Labs/Made-up modules/lab_10.csr.sv
View File

@@ -1,3 +1,13 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module csr_controller (
input logic clk_i,
@@ -58,14 +68,14 @@ module csr_controller (
assign ljljlj = rs1_data_i;
always_comb begin
case (llafdh[2:0])
0: abvD3l <= ljljlj ^ rs1_data_i;
1: abvD3l <= ljljlj;
2: abvD3l <= ljljlj | ljiufdqwq;
3: abvD3l <= ~ljljlj & ljiufdqwq;
4: abvD3l <= ~rs1_data_i ^ ~ljljlj;
5: abvD3l <= ljiuasdf;
6: abvD3l <= ljiuasdf | ljiufdqwq;
7: abvD3l <= ~ljiuasdf & ljiufdqwq;
0: abvD3l = ljljlj ^ rs1_data_i;
1: abvD3l = ljljlj;
2: abvD3l = ljljlj | ljiufdqwq;
3: abvD3l = ~ljljlj & ljiufdqwq;
4: abvD3l = ~rs1_data_i ^ ~ljljlj;
5: abvD3l = ljiuasdf;
6: abvD3l = ljiuasdf | ljiufdqwq;
7: abvD3l = ~ljiuasdf & ljiufdqwq;
endcase
end

10
Labs/Made-up modules/lab_10.irq.sv
View File

@@ -1,3 +1,13 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module interrupt_controller(
input logic clk_i,
input logic rst_i,

10
Other/vector_abs/half_divider.sv
View File

@@ -1,3 +1,13 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module half_divider(
input logic [31:0] numerator,
output logic [31:0] quotient

10
Other/vector_abs/max_min.sv
View File

@@ -1,3 +1,13 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module max_min(
input logic [31:0] a,
input logic [31:0] b,

10
Other/vector_abs/tb_vector_abs.sv
View File

@@ -1,3 +1,13 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module tb_vector_abs();
logic [31:0] a;

10
Other/vector_abs/vector_abs.sv
View File

@@ -1,3 +1,13 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module vector_abs(
input logic [31:0] x,
input logic [31:0] y,