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38 lines
1.1 KiB
Systemverilog
38 lines
1.1 KiB
Systemverilog
/* -----------------------------------------------------------------------------
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* Project Name : Architectures of Processor Systems (APS) lab work
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* Organization : National Research University of Electronic Technology (MIET)
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* Department : Institute of Microdevices and Control Systems
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* Author(s) : Andrei Solodovnikov
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* Email(s) : hepoh@org.miet.ru
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See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
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* ------------------------------------------------------------------------------
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*/
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package alu_opcodes_pkg;
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localparam ALU_OP_WIDTH = 5;
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localparam ALU_ADD = 5'b00000;
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localparam ALU_SUB = 5'b01000;
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localparam ALU_XOR = 5'b00100;
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localparam ALU_OR = 5'b00110;
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localparam ALU_AND = 5'b00111;
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// shifts
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localparam ALU_SRA = 5'b01101;
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localparam ALU_SRL = 5'b00101;
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localparam ALU_SLL = 5'b00001;
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// comparisons
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localparam ALU_LTS = 5'b11100;
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localparam ALU_LTU = 5'b11110;
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localparam ALU_GES = 5'b11101;
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localparam ALU_GEU = 5'b11111;
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localparam ALU_EQ = 5'b11000;
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localparam ALU_NE = 5'b11001;
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// set lower than operations
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localparam ALU_SLTS = 5'b00010;
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localparam ALU_SLTU = 5'b00011;
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endpackage |