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45 lines
1.3 KiB
Systemverilog
45 lines
1.3 KiB
Systemverilog
/* -----------------------------------------------------------------------------
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* Project Name : Architectures of Processor Systems (APS) lab work
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* Organization : National Research University of Electronic Technology (MIET)
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* Department : Institute of Microdevices and Control Systems
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* Author(s) : Andrei Solodovnikov
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* Email(s) : hepoh@org.miet.ru
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See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
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* ------------------------------------------------------------------------------
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*/
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module tb_fulladder4();
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logic [3:0] tb_a_i;
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logic [3:0] tb_b_i;
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logic tb_carry_i;
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logic tb_carry_o;
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logic [3:0] tb_sum_o;
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logic [8:0] test_case;
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fulladder4 DUT (
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.a_i(tb_a_i),
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.b_i(tb_b_i),
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.sum_o(tb_sum_o),
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.carry_i(tb_carry_i),
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.carry_o(tb_carry_o)
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);
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assign {tb_a_i, tb_b_i, tb_carry_i} = test_case;
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initial begin
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$display("Test has been started");
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$display( "\n\n==========================\nCLICK THE BUTTON 'Run All'\n==========================\n"); $stop();
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#5ns;
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test_case = 3'd0;
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repeat(512) begin
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#5ns;
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test_case++;
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end
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$display("\nTest has been finished\n");
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$finish();
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end
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endmodule
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