From 3dcb0b76f91584916ac20c562a28d9980af36460 Mon Sep 17 00:00:00 2001 From: Andrei Solodovnikov Date: Wed, 21 Feb 2024 11:48:18 +0300 Subject: [PATCH] =?UTF-8?q?=D0=94=D0=BE=D0=B1=D0=B0=D0=B2=D0=BB=D0=B5?= =?UTF-8?q?=D0=BD=D0=B8=D0=B5=20=D0=BA=D1=80=D0=B5=D0=B4=D0=B8=D1=82=D0=BE?= =?UTF-8?q?=D0=B2=20=D0=B2=20=D0=B8=D1=81=D1=85=D0=BE=D0=B4=D0=BD=D0=B8?= =?UTF-8?q?=D0=BA=D0=B8?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Labs/01. Adder/board files/nexys_adder.sv | 10 ++++++ Labs/01. Adder/tb_fulladder.sv | 17 +++++----- Labs/01. Adder/tb_fulladder32.sv | 17 +++++----- Labs/01. Adder/tb_fulladder4.sv | 17 +++++----- .../alu_opcodes_pkg.sv | 10 ++++++ .../board files/nexys_alu.sv | 4 +-- Labs/02. Arithmetic-logic unit/tb_alu.sv | 18 +++++----- .../board files/nexys_rf_riscv.sv | 34 ++++++++++++------- .../tb_data_mem.sv | 18 +++++----- .../tb_instr_mem.sv | 18 +++++----- .../tb_rf_riscv.sv | 18 +++++----- .../board files/nexys_cybercobra.sv | 14 ++++++-- .../board files/nexys_cybercobra_demo.sv | 14 ++++++-- .../tb_cybercobra.sv | 28 +++++++-------- Labs/05. Main decoder/alu_opcodes_pkg.sv | 10 ++++++ Labs/05. Main decoder/csr_pkg.sv | 10 ++++++ Labs/05. Main decoder/riscv_pkg.sv | 10 ++++++ Labs/05. Main decoder/tb_decoder_riscv.sv | 19 +++++------ Labs/06. Datapath/alu_opcodes_pkg.sv | 10 ++++++ .../board files/nexys_riscv_unit.sv | 18 +++++++--- Labs/06. Datapath/csr_pkg.sv | 12 ++++++- Labs/06. Datapath/riscv_pkg.sv | 10 ++++++ Labs/06. Datapath/tb_riscv_unit.sv | 18 +++++----- Labs/08. Load-store unit/tb_lsu.sv | 18 +++++----- Labs/10. Interrupt subsystem/csr_pkg.sv | 12 ++++++- Labs/10. Interrupt subsystem/tb_csr.sv | 18 +++++----- Labs/10. Interrupt subsystem/tb_irq.sv | 19 +++++------ Labs/11. Interrupt integration/tb_irq_unit.sv | 19 +++++------ Labs/12. Daisy chain/tb_daisy_chain.sv | 19 +++++------ .../firmware/software/ps2_hex.S | 10 ++++++ .../firmware/software/ps2_vga.S | 10 ++++++ .../firmware/software/rx_hex.S | 10 ++++++ .../firmware/software/rx_led.S | 10 ++++++ .../firmware/software/rx_tx.S | 10 ++++++ .../firmware/software/sw_led.S | 10 ++++++ .../peripheral modules/PS2Receiver.sv | 23 +++++++++++++ .../peripheral modules/hex_digits.sv | 10 ++++++ .../peripheral modules/uart_rx.sv | 10 ++++++ .../peripheral modules/uart_tx.sv | 10 ++++++ .../peripheral modules/vgachargen.sv | 10 ++++++ .../peripheral modules/vgachargen_pkg.sv | 10 ++++++ Labs/13. Peripheral units/sys_clk_rst_gen.sv | 10 ++++++ Labs/13. Peripheral units/tb_riscv_unit.sv | 19 +++++------ Labs/14. Programming/linker_script.ld | 10 ++++++ Labs/14. Programming/platform.h | 10 ++++++ Labs/14. Programming/startup.S | 10 ++++++ Labs/15. Programming device/flash.py | 10 ++++++ Labs/15. Programming device/tb_bluster.sv | 19 +++++------ Labs/15. Programming device/tb_top_asic.sv | 19 +++++------ Labs/16. Coremark/Makefile | 10 ++++++ Labs/16. Coremark/linker_script.ld | 10 ++++++ Labs/16. Coremark/startup.S | 10 ++++++ Labs/16. Coremark/tb_coremark.sv | 19 +++++------ Labs/16. Coremark/tb_timer.sv | 19 +++++------ Labs/Made-up modules/lab_01.fulladder32.sv | 10 ++++++ Labs/Made-up modules/lab_03.data_mem.sv | 10 ++++++ Labs/Made-up modules/lab_03.instr_mem.sv | 10 ++++++ Labs/Made-up modules/lab_03.register_file.sv | 10 ++++++ Labs/Made-up modules/lab_05.decoder.sv | 18 +++++----- Labs/Made-up modules/lab_07.ext_mem.sv | 18 +++++----- Labs/Made-up modules/lab_08.lsu.sv | 18 +++++----- Labs/Made-up modules/lab_10.csr.sv | 26 +++++++++----- Labs/Made-up modules/lab_10.irq.sv | 10 ++++++ Other/vector_abs/half_divider.sv | 10 ++++++ Other/vector_abs/max_min.sv | 10 ++++++ Other/vector_abs/tb_vector_abs.sv | 10 ++++++ Other/vector_abs/vector_abs.sv | 10 ++++++ 67 files changed, 686 insertions(+), 251 deletions(-) diff --git a/Labs/01. Adder/board files/nexys_adder.sv b/Labs/01. Adder/board files/nexys_adder.sv index 3fe6e1a..356266c 100644 --- a/Labs/01. Adder/board files/nexys_adder.sv +++ b/Labs/01. Adder/board files/nexys_adder.sv @@ -1,3 +1,13 @@ +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Nikita Bulavin +* Email(s) : nekkit6@edu.miet.ru + +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ module nexys_adder( input CLK100, input resetn, diff --git a/Labs/01. Adder/tb_fulladder.sv b/Labs/01. Adder/tb_fulladder.sv index ff6e1c1..002574c 100644 --- a/Labs/01. Adder/tb_fulladder.sv +++ b/Labs/01. Adder/tb_fulladder.sv @@ -1,12 +1,13 @@ -////////////////////////////////////////////////////////////////////////////////// -// Company: MIET -// Engineer: Andrei Solodovnikov +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Andrei Solodovnikov +* Email(s) : hepoh@org.miet.ru -// Module Name: tb_fulladder -// Project Name: RISCV_practicum -// Target Devices: Nexys A7-100T -// Description: tb for 1-bit fulladder -////////////////////////////////////////////////////////////////////////////////// +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ module tb_fulladder(); diff --git a/Labs/01. Adder/tb_fulladder32.sv b/Labs/01. Adder/tb_fulladder32.sv index 311cb78..1c7fb9c 100644 --- a/Labs/01. Adder/tb_fulladder32.sv +++ b/Labs/01. Adder/tb_fulladder32.sv @@ -1,12 +1,13 @@ -////////////////////////////////////////////////////////////////////////////////// -// Company: MIET -// Engineer: Andrei Solodovnikov +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Andrei Solodovnikov +* Email(s) : hepoh@org.miet.ru -// Module Name: tb_fulladder32 -// Project Name: RISCV_practicum -// Target Devices: Nexys A7-100T -// Description: tb for 32-bit fulladder -////////////////////////////////////////////////////////////////////////////////// +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ module tb_fulladder32(); diff --git a/Labs/01. Adder/tb_fulladder4.sv b/Labs/01. Adder/tb_fulladder4.sv index ccf7925..cadb905 100644 --- a/Labs/01. Adder/tb_fulladder4.sv +++ b/Labs/01. Adder/tb_fulladder4.sv @@ -1,12 +1,13 @@ -////////////////////////////////////////////////////////////////////////////////// -// Company: MIET -// Engineer: Andrei Solodovnikov +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Andrei Solodovnikov +* Email(s) : hepoh@org.miet.ru -// Module Name: tb_fulladder4 -// Project Name: RISCV_practicum -// Target Devices: Nexys A7-100T -// Description: tb for 4-bit fulladder -////////////////////////////////////////////////////////////////////////////////// +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ module tb_fulladder4(); diff --git a/Labs/02. Arithmetic-logic unit/alu_opcodes_pkg.sv b/Labs/02. Arithmetic-logic unit/alu_opcodes_pkg.sv index d09db8f..9ec054c 100644 --- a/Labs/02. Arithmetic-logic unit/alu_opcodes_pkg.sv +++ b/Labs/02. Arithmetic-logic unit/alu_opcodes_pkg.sv @@ -1,3 +1,13 @@ +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Andrei Solodovnikov +* Email(s) : hepoh@org.miet.ru + +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ package alu_opcodes_pkg; localparam ALU_OP_WIDTH = 5; diff --git a/Labs/02. Arithmetic-logic unit/board files/nexys_alu.sv b/Labs/02. Arithmetic-logic unit/board files/nexys_alu.sv index 5e2707e..6f35552 100644 --- a/Labs/02. Arithmetic-logic unit/board files/nexys_alu.sv +++ b/Labs/02. Arithmetic-logic unit/board files/nexys_alu.sv @@ -1,15 +1,13 @@ /* ----------------------------------------------------------------------------- * Project Name : Architectures of Processor Systems (APS) lab work -* File : nexys_alu.sv * Organization : National Research University of Electronic Technology (MIET) * Department : Institute of Microdevices and Control Systems * Author(s) : Alexander Kharlamov * Email(s) : sasha_xarlamov@org.miet.ru -See LICENSE file for licensing details. +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. * ------------------------------------------------------------------------------ */ - module nexys_alu( input logic clk_i, input logic arstn_i, diff --git a/Labs/02. Arithmetic-logic unit/tb_alu.sv b/Labs/02. Arithmetic-logic unit/tb_alu.sv index d42646b..817611d 100644 --- a/Labs/02. Arithmetic-logic unit/tb_alu.sv +++ b/Labs/02. Arithmetic-logic unit/tb_alu.sv @@ -1,13 +1,13 @@ -////////////////////////////////////////////////////////////////////////////////// -// Company: MIET -// Engineer: Nikita Bulavin - -// Module Name: tb_miriscv_alu -// Project Name: RISCV_practicum -// Target Devices: Nexys A7-100T -// Description: tb for miriscv alu -////////////////////////////////////////////////////////////////////////////////// +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Nikita Bulavin +* Email(s) : nekkit6@edu.miet.ru +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ module tb_miriscv_alu(); import alu_opcodes_pkg::*; diff --git a/Labs/03. Register file and memory/board files/nexys_rf_riscv.sv b/Labs/03. Register file and memory/board files/nexys_rf_riscv.sv index 5a7c7df..5505fe4 100644 --- a/Labs/03. Register file and memory/board files/nexys_rf_riscv.sv +++ b/Labs/03. Register file and memory/board files/nexys_rf_riscv.sv @@ -1,14 +1,24 @@ +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Nikita Bulavin +* Email(s) : nekkit6@edu.miet.ru + +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ module nexys_rf_riscv( input CLK100, input resetn, - input BTND, BTNU, BTNL, BTNR, BTNC, + input BTND, BTNU, BTNL, BTNR, BTNC, input [15:0] SW, output [15:0] LED, output CA, CB, CC, CD, CE, CF, CG, DP, output [7:0] AN, output LED16_B, LED16_G, LED16_R, LED17_B, LED17_G, LED17_R ); - + wire [31:0] WD3; wire WE; wire [31:0] RD1; @@ -75,40 +85,40 @@ always @(posedge CLK100) begin a1 <= BTNL? SW[4:0]: a1; a2 <= BTNC? SW[4:0]: a2; a3 <= BTNR? SW[4:0]: a3; - + rd1 <= BTNU? RD1: rd1; rd2 <= BTNU? RD2: rd2; - + case (1'b0) - ANreg[0]: begin + ANreg[0]: begin semseg <= (rd2) % 5'h10; //DPr <= 1'b1; end - ANreg[1]: begin + ANreg[1]: begin semseg <= (rd2 / 'h10) % 5'h10; //DPr <= 1'b1; end - ANreg[2]: begin + ANreg[2]: begin semseg <= (rd2 / 'h100) % 5'h10; //DPr <= 1'b1; end - ANreg[3]: begin + ANreg[3]: begin semseg <= (rd2 / 'h1000) % 5'h10; //DPr <= 1'b1; end - ANreg[4]: begin + ANreg[4]: begin semseg <= (rd1) % 5'h10; //DPr <= 1'b1; end - ANreg[5]: begin + ANreg[5]: begin semseg <= (rd1 / 'h10) % 5'h10; //DPr <= 1'b1; end - ANreg[6]: begin + ANreg[6]: begin semseg <= (rd1 / 'h100) % 5'h10; //DPr <= 1'b1; end - ANreg[7]: begin + ANreg[7]: begin semseg <= (rd1 / 'h1000) % 5'h10; //DPr <= 1'b1; end diff --git a/Labs/03. Register file and memory/tb_data_mem.sv b/Labs/03. Register file and memory/tb_data_mem.sv index b679bfd..a23793f 100644 --- a/Labs/03. Register file and memory/tb_data_mem.sv +++ b/Labs/03. Register file and memory/tb_data_mem.sv @@ -1,13 +1,13 @@ -////////////////////////////////////////////////////////////////////////////////// -// Company: MIET -// Engineer: Nikita Bulavin - -// Module Name: tb_data_mem -// Project Name: RISCV_practicum -// Target Devices: Nexys A7-100T -// Description: tb for data memory -////////////////////////////////////////////////////////////////////////////////// +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Nikita Bulavin +* Email(s) : nekkit6@edu.miet.ru +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ module tb_data_mem(); parameter ADDR_SIZE = 16384; diff --git a/Labs/03. Register file and memory/tb_instr_mem.sv b/Labs/03. Register file and memory/tb_instr_mem.sv index c9a3359..74c058d 100644 --- a/Labs/03. Register file and memory/tb_instr_mem.sv +++ b/Labs/03. Register file and memory/tb_instr_mem.sv @@ -1,13 +1,13 @@ -////////////////////////////////////////////////////////////////////////////////// -// Company: MIET -// Engineer: Nikita Bulavin - -// Module Name: tb_instr_mem -// Project Name: RISCV_practicum -// Target Devices: Nexys A7-100T -// Description: tb for instruction memory -////////////////////////////////////////////////////////////////////////////////// +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Nikita Bulavin +* Email(s) : nekkit6@edu.miet.ru +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ module tb_instr_mem(); parameter ADDR_SIZE = 4096; diff --git a/Labs/03. Register file and memory/tb_rf_riscv.sv b/Labs/03. Register file and memory/tb_rf_riscv.sv index d572f18..9662494 100644 --- a/Labs/03. Register file and memory/tb_rf_riscv.sv +++ b/Labs/03. Register file and memory/tb_rf_riscv.sv @@ -1,13 +1,13 @@ -////////////////////////////////////////////////////////////////////////////////// -// Company: MIET -// Engineer: Nikita Bulavin - -// Module Name: tb_rf_riscv -// Project Name: RISCV_practicum -// Target Devices: Nexys A7-100T -// Description: tb for RISC-V register file -////////////////////////////////////////////////////////////////////////////////// +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Nikita Bulavin +* Email(s) : nekkit6@edu.miet.ru +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ module tb_rf_riscv(); logic CLK; diff --git a/Labs/04. Primitive programmable device/board files/nexys_cybercobra.sv b/Labs/04. Primitive programmable device/board files/nexys_cybercobra.sv index 27b30fd..acd1107 100644 --- a/Labs/04. Primitive programmable device/board files/nexys_cybercobra.sv +++ b/Labs/04. Primitive programmable device/board files/nexys_cybercobra.sv @@ -1,12 +1,22 @@ +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Nikita Bulavin +* Email(s) : nekkit6@edu.miet.ru + +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ module nexys_CYBERcobra_dz( input CLK100, input resetn, input BTND, input [15:0] SW, - output CA, CB, CC, CD, CE, CF, CG, + output CA, CB, CC, CD, CE, CF, CG, output [7:0] AN ); - + CYBERcobra dut( .clk_i(btn), .rst_i(!resetn), diff --git a/Labs/04. Primitive programmable device/board files/nexys_cybercobra_demo.sv b/Labs/04. Primitive programmable device/board files/nexys_cybercobra_demo.sv index e0bc145..91c83e3 100644 --- a/Labs/04. Primitive programmable device/board files/nexys_cybercobra_demo.sv +++ b/Labs/04. Primitive programmable device/board files/nexys_cybercobra_demo.sv @@ -1,12 +1,22 @@ +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Nikita Bulavin +* Email(s) : nekkit6@edu.miet.ru + +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ module nexys_CYBERcobra( input CLK100, input resetn, input BTND, input [15:0] SW, - output CA, CB, CC, CD, CE, CF, CG, + output CA, CB, CC, CD, CE, CF, CG, output [7:0] AN ); - + CYBERcobra dut( .clk_i(CLK100), .rst_i(!resetn), diff --git a/Labs/04. Primitive programmable device/tb_cybercobra.sv b/Labs/04. Primitive programmable device/tb_cybercobra.sv index aa688b0..87c7226 100644 --- a/Labs/04. Primitive programmable device/tb_cybercobra.sv +++ b/Labs/04. Primitive programmable device/tb_cybercobra.sv @@ -1,22 +1,22 @@ -////////////////////////////////////////////////////////////////////////////////// -// Company: MIET -// Engineer: Nikita Bulavin - -// Module Name: tb_cybercobra -// Project Name: RISCV_practicum -// Target Devices: Nexys A7-100T -// Description: tb for CYBERcobra 3000 Pro 2.1 -////////////////////////////////////////////////////////////////////////////////// +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Nikita Bulavin +* Email(s) : nekkit6@edu.miet.ru +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ module tb_CYBERcobra(); - + CYBERcobra dut( .clk_i(clk), .rst_i(rstn), .sw_i (sw_i ), .out_o(OUT) ); - + wire [31:0] OUT; reg clk; reg rstn; @@ -24,8 +24,8 @@ module tb_CYBERcobra(); initial clk <= 0; always #5 clk = ~clk; - - initial begin + + initial begin $display( "\nStart test: \n\n===============================================\nAdd CYBERcobra signals to the waveform and then\nCLICK THE BUTTON 'Run All'\n===============================================\n"); $stop(); rstn = 1'b1; #10; @@ -37,5 +37,5 @@ module tb_CYBERcobra(); $display("\n The test is over \n See the internal signals of the CYBERcobra on the waveform \n"); $finish; end - + endmodule diff --git a/Labs/05. Main decoder/alu_opcodes_pkg.sv b/Labs/05. Main decoder/alu_opcodes_pkg.sv index d09db8f..9ec054c 100644 --- a/Labs/05. Main decoder/alu_opcodes_pkg.sv +++ b/Labs/05. Main decoder/alu_opcodes_pkg.sv @@ -1,3 +1,13 @@ +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Andrei Solodovnikov +* Email(s) : hepoh@org.miet.ru + +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ package alu_opcodes_pkg; localparam ALU_OP_WIDTH = 5; diff --git a/Labs/05. Main decoder/csr_pkg.sv b/Labs/05. Main decoder/csr_pkg.sv index a0fefeb..5a295da 100644 --- a/Labs/05. Main decoder/csr_pkg.sv +++ b/Labs/05. Main decoder/csr_pkg.sv @@ -1,3 +1,13 @@ +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Andrei Solodovnikov +* Email(s) : hepoh@org.miet.ru + +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ package csr_pkg; localparam CSR_RW = 3'b001; diff --git a/Labs/05. Main decoder/riscv_pkg.sv b/Labs/05. Main decoder/riscv_pkg.sv index 9f68d24..4b977b1 100644 --- a/Labs/05. Main decoder/riscv_pkg.sv +++ b/Labs/05. Main decoder/riscv_pkg.sv @@ -1,3 +1,13 @@ +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Andrei Solodovnikov +* Email(s) : hepoh@org.miet.ru + +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ package riscv_pkg; import alu_opcodes_pkg::*; diff --git a/Labs/05. Main decoder/tb_decoder_riscv.sv b/Labs/05. Main decoder/tb_decoder_riscv.sv index dd7dcd3..a8492bb 100644 --- a/Labs/05. Main decoder/tb_decoder_riscv.sv +++ b/Labs/05. Main decoder/tb_decoder_riscv.sv @@ -1,14 +1,13 @@ -////////////////////////////////////////////////////////////////////////////////// -// Company: MIET -// Engineer: Nikita Bulavin - -// Module Name: tb_decoder_riscv -// Project Name: RISCV_practicum -// Target Devices: Nexys A7-100T - -// Description: tb for decoder riscv -////////////////////////////////////////////////////////////////////////////////// +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Nikita Bulavin +* Email(s) : nekkit6@edu.miet.ru +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ module tb_decoder_riscv(); import riscv_pkg::*; diff --git a/Labs/06. Datapath/alu_opcodes_pkg.sv b/Labs/06. Datapath/alu_opcodes_pkg.sv index d09db8f..9ec054c 100644 --- a/Labs/06. Datapath/alu_opcodes_pkg.sv +++ b/Labs/06. Datapath/alu_opcodes_pkg.sv @@ -1,3 +1,13 @@ +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Andrei Solodovnikov +* Email(s) : hepoh@org.miet.ru + +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ package alu_opcodes_pkg; localparam ALU_OP_WIDTH = 5; diff --git a/Labs/06. Datapath/board files/nexys_riscv_unit.sv b/Labs/06. Datapath/board files/nexys_riscv_unit.sv index 4195730..f5d5cf1 100644 --- a/Labs/06. Datapath/board files/nexys_riscv_unit.sv +++ b/Labs/06. Datapath/board files/nexys_riscv_unit.sv @@ -1,11 +1,21 @@ +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Nikita Bulavin +* Email(s) : nekkit6@edu.miet.ru + +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ module nexys_riscv_unit( input CLK100, input resetn, input BTND, - output CA, CB, CC, CD, CE, CF, CG, + output CA, CB, CC, CD, CE, CF, CG, output [7:0] AN ); - + riscv_unit unit( .clk_i(btn), .rst_i(!resetn) @@ -14,7 +24,7 @@ module nexys_riscv_unit( wire [31:0] instr_addr; wire [31:0] instr; reg btn; - + assign instr_addr = unit.core.instr_addr_o; assign instr = unit.core.instr_i; @@ -140,7 +150,7 @@ module nexys_riscv_unit( endcase end end - + end endmodule diff --git a/Labs/06. Datapath/csr_pkg.sv b/Labs/06. Datapath/csr_pkg.sv index c863719..ca5124f 100644 --- a/Labs/06. Datapath/csr_pkg.sv +++ b/Labs/06. Datapath/csr_pkg.sv @@ -1,3 +1,13 @@ +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Andrei Solodovnikov +* Email(s) : hepoh@org.miet.ru + +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ package csr_pkg; localparam CSR_RW = 3'b001; @@ -6,7 +16,7 @@ package csr_pkg; localparam CSR_RWI = 3'b101; localparam CSR_RSI = 3'b110; localparam CSR_RCI = 3'b111; - + localparam MIE_ADDR = 12'h304; localparam MTVEC_ADDR = 12'h305; localparam MSCRATCH_ADDR = 12'h340; diff --git a/Labs/06. Datapath/riscv_pkg.sv b/Labs/06. Datapath/riscv_pkg.sv index df56313..4aa4891 100644 --- a/Labs/06. Datapath/riscv_pkg.sv +++ b/Labs/06. Datapath/riscv_pkg.sv @@ -1,3 +1,13 @@ +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Andrei Solodovnikov +* Email(s) : hepoh@org.miet.ru + +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ package riscv_pkg; import alu_opcodes_pkg::*; diff --git a/Labs/06. Datapath/tb_riscv_unit.sv b/Labs/06. Datapath/tb_riscv_unit.sv index d57f9ca..07abaf0 100644 --- a/Labs/06. Datapath/tb_riscv_unit.sv +++ b/Labs/06. Datapath/tb_riscv_unit.sv @@ -1,13 +1,13 @@ -////////////////////////////////////////////////////////////////////////////////// -// Company: MIET -// Engineer: Nikita Bulavin - -// Module Name: tb_riscv_unit -// Project Name: RISCV_practicum -// Target Devices: Nexys A7-100T -// Description: tb for datapath -////////////////////////////////////////////////////////////////////////////////// +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Nikita Bulavin +* Email(s) : nekkit6@edu.miet.ru +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ module tb_riscv_unit(); reg clk; diff --git a/Labs/08. Load-store unit/tb_lsu.sv b/Labs/08. Load-store unit/tb_lsu.sv index f0aa9b4..f72da0e 100644 --- a/Labs/08. Load-store unit/tb_lsu.sv +++ b/Labs/08. Load-store unit/tb_lsu.sv @@ -1,13 +1,13 @@ -////////////////////////////////////////////////////////////////////////////////// -// Company: MIET -// Engineer: Andrei Solodovnikov +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Andrei Solodovnikov +* Email(s) : hepoh@org.miet.ru -// Module Name: lsu_testbench -// Project Name: RISCV_practicum -// Target Devices: Nexys A7-100T -// Description: tb for Load&Store module -// -////////////////////////////////////////////////////////////////////////////////// +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ module tb_lsu(); import riscv_pkg::*; logic clk_i ; diff --git a/Labs/10. Interrupt subsystem/csr_pkg.sv b/Labs/10. Interrupt subsystem/csr_pkg.sv index bf37986..5a295da 100644 --- a/Labs/10. Interrupt subsystem/csr_pkg.sv +++ b/Labs/10. Interrupt subsystem/csr_pkg.sv @@ -1,3 +1,13 @@ +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Andrei Solodovnikov +* Email(s) : hepoh@org.miet.ru + +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ package csr_pkg; localparam CSR_RW = 3'b001; @@ -6,7 +16,7 @@ package csr_pkg; localparam CSR_RWI = 3'b101; localparam CSR_RSI = 3'b110; localparam CSR_RCI = 3'b111; - + localparam MIE_ADDR = 12'h304; localparam MTVEC_ADDR = 12'h305; localparam MSCRATCH_ADDR = 12'h340; diff --git a/Labs/10. Interrupt subsystem/tb_csr.sv b/Labs/10. Interrupt subsystem/tb_csr.sv index 9dc6529..141c5e6 100644 --- a/Labs/10. Interrupt subsystem/tb_csr.sv +++ b/Labs/10. Interrupt subsystem/tb_csr.sv @@ -1,13 +1,13 @@ -////////////////////////////////////////////////////////////////////////////////// -// Company: MIET -// Engineer: Daniil Strelkov +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Daniil Strelkov +* Email(s) : @edu.miet.ru -// Module Name: tb_csr -// Project Name: RISCV_practicum -// Target Devices: Nexys A7-100T -// Description: tb for CSR controller -// -////////////////////////////////////////////////////////////////////////////////// +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ module tb_csr(); logic clk_i; diff --git a/Labs/10. Interrupt subsystem/tb_irq.sv b/Labs/10. Interrupt subsystem/tb_irq.sv index ad744bb..8431466 100644 --- a/Labs/10. Interrupt subsystem/tb_irq.sv +++ b/Labs/10. Interrupt subsystem/tb_irq.sv @@ -1,14 +1,13 @@ -////////////////////////////////////////////////////////////////////////////////// -// Company: MIET -// Engineer: Daniil Strelkov - -// Module Name: tb_irq -// Project Name: RISCV_practicum -// Target Devices: Nexys A7-100T -// Description: tb for interrupt controller -// -////////////////////////////////////////////////////////////////////////////////// +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Daniil Strelkov +* Email(s) : @edu.miet.ru +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ module tb_irq(); logic clk_i; logic rst_i; diff --git a/Labs/11. Interrupt integration/tb_irq_unit.sv b/Labs/11. Interrupt integration/tb_irq_unit.sv index 3b23002..6a22914 100644 --- a/Labs/11. Interrupt integration/tb_irq_unit.sv +++ b/Labs/11. Interrupt integration/tb_irq_unit.sv @@ -1,14 +1,13 @@ -////////////////////////////////////////////////////////////////////////////////// -// Company: MIET -// Engineer: Andrei Solodovnikov - -// Module Name: tb_riscv_unit -// Project Name: RISCV_practicum -// Target Devices: Nexys A7-100T -// Description: tb for riscv unit with irq support - -////////////////////////////////////////////////////////////////////////////////// +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Andrei Solodovnikov +* Email(s) : hepoh@org.miet.ru +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ module tb_irq_unit(); reg clk; diff --git a/Labs/12. Daisy chain/tb_daisy_chain.sv b/Labs/12. Daisy chain/tb_daisy_chain.sv index f61f752..41b09c7 100644 --- a/Labs/12. Daisy chain/tb_daisy_chain.sv +++ b/Labs/12. Daisy chain/tb_daisy_chain.sv @@ -1,14 +1,13 @@ -////////////////////////////////////////////////////////////////////////////////// -// Company: MIET -// Engineer: Solodovnikov Andrei - -// Module Name: tb_daisy_chain -// Project Name: RISCV_practicum -// Target Devices: Nexys A7-100T -// Description: tb for daisy chain -// -////////////////////////////////////////////////////////////////////////////////// +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Andrei Solodovnikov +* Email(s) : hepoh@org.miet.ru +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ module tb_daisy_chain(); logic clk_i, rst_i, ready_i, irq_ret_i; diff --git a/Labs/13. Peripheral units/firmware/software/ps2_hex.S b/Labs/13. Peripheral units/firmware/software/ps2_hex.S index 08f29bc..28170d9 100644 --- a/Labs/13. Peripheral units/firmware/software/ps2_hex.S +++ b/Labs/13. Peripheral units/firmware/software/ps2_hex.S @@ -1,3 +1,13 @@ +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Andrei Solodovnikov +* Email(s) : hepoh@org.miet.ru + +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ _start: # Инициализируем начальные значения регистров 0: 030000b7 li x1 , 0x03000000 # сохраняем базовый адрес клавиатуры diff --git a/Labs/13. Peripheral units/firmware/software/ps2_vga.S b/Labs/13. Peripheral units/firmware/software/ps2_vga.S index 67e6ee8..e10e61c 100644 --- a/Labs/13. Peripheral units/firmware/software/ps2_vga.S +++ b/Labs/13. Peripheral units/firmware/software/ps2_vga.S @@ -1,3 +1,13 @@ +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Andrei Solodovnikov +* Email(s) : hepoh@org.miet.ru + +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ _start: # Инициализируем начальные значения регистров 0: 030000b7 li x1, 0x03000000 # сохраняем базовый адрес клавиатуры diff --git a/Labs/13. Peripheral units/firmware/software/rx_hex.S b/Labs/13. Peripheral units/firmware/software/rx_hex.S index 7a2b166..f43230f 100644 --- a/Labs/13. Peripheral units/firmware/software/rx_hex.S +++ b/Labs/13. Peripheral units/firmware/software/rx_hex.S @@ -1,3 +1,13 @@ +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Andrei Solodovnikov +* Email(s) : hepoh@org.miet.ru + +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ _start: # Инициализируем начальные значения регистров 0: 050000b7 li x1 , 0x05000000 # сохраняем базовый адрес uart_rx diff --git a/Labs/13. Peripheral units/firmware/software/rx_led.S b/Labs/13. Peripheral units/firmware/software/rx_led.S index 296cceb..b33c759 100644 --- a/Labs/13. Peripheral units/firmware/software/rx_led.S +++ b/Labs/13. Peripheral units/firmware/software/rx_led.S @@ -1,3 +1,13 @@ +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Andrei Solodovnikov +* Email(s) : hepoh@org.miet.ru + +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ _start: # Инициализируем начальные значения регистров 0: 050000b7 li x1, 0x05000000 # сохраняем базовый адрес uart_rx diff --git a/Labs/13. Peripheral units/firmware/software/rx_tx.S b/Labs/13. Peripheral units/firmware/software/rx_tx.S index 51f4351..b7003e5 100644 --- a/Labs/13. Peripheral units/firmware/software/rx_tx.S +++ b/Labs/13. Peripheral units/firmware/software/rx_tx.S @@ -1,3 +1,13 @@ +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Andrei Solodovnikov +* Email(s) : hepoh@org.miet.ru + +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ _start: # Инициализируем начальные значения регистров 0: 050000b7 li x1 , 0x05000000 # сохраняем базовый адрес uart_rx diff --git a/Labs/13. Peripheral units/firmware/software/sw_led.S b/Labs/13. Peripheral units/firmware/software/sw_led.S index 08e5810..17ec16c 100644 --- a/Labs/13. Peripheral units/firmware/software/sw_led.S +++ b/Labs/13. Peripheral units/firmware/software/sw_led.S @@ -1,3 +1,13 @@ +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Andrei Solodovnikov +* Email(s) : hepoh@org.miet.ru + +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ _start: # Инициализируем начальные значения регистров 0: 010000b7 li x1, 0x01000000 # сохраняем базовый адрес переключателей diff --git a/Labs/13. Peripheral units/peripheral modules/PS2Receiver.sv b/Labs/13. Peripheral units/peripheral modules/PS2Receiver.sv index d90f3f2..80e4f56 100644 --- a/Labs/13. Peripheral units/peripheral modules/PS2Receiver.sv +++ b/Labs/13. Peripheral units/peripheral modules/PS2Receiver.sv @@ -1,3 +1,26 @@ +////////////////////////////////////////////////////////////////////////////////// +// Company: Digilent Inc. +// Engineer: Thomas Kappenman +// +// Create Date: 03/03/2015 09:33:36 PM +// Design Name: +// Module Name: PS2Receiver +// Project Name: Nexys4DDR Keyboard Demo +// Target Devices: Nexys4DDR +// Tool Versions: +// Description: PS2 Receiver module used to shift in keycodes from a keyboard plugged into the PS2 port +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// Modified in 2023 by engineers of +// National Research University of Electronic Technology +// Nikita Bulavin and Andrei Solodovnikov +// +////////////////////////////////////////////////////////////////////////////////// + module PS2Receiver( input logic clk_i, input logic rst_i, diff --git a/Labs/13. Peripheral units/peripheral modules/hex_digits.sv b/Labs/13. Peripheral units/peripheral modules/hex_digits.sv index d15caee..c0ad449 100644 --- a/Labs/13. Peripheral units/peripheral modules/hex_digits.sv +++ b/Labs/13. Peripheral units/peripheral modules/hex_digits.sv @@ -1,3 +1,13 @@ +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Nikita Bulavin +* Email(s) : nekkit6@edu.miet.ru + +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ module hex_digits( input logic clk_i, input logic rst_i, diff --git a/Labs/13. Peripheral units/peripheral modules/uart_rx.sv b/Labs/13. Peripheral units/peripheral modules/uart_rx.sv index 53b2a2b..c6529e0 100644 --- a/Labs/13. Peripheral units/peripheral modules/uart_rx.sv +++ b/Labs/13. Peripheral units/peripheral modules/uart_rx.sv @@ -8,6 +8,16 @@ // CONDITIONS OF ANY KIND, either express or implied. See the License for the // specific language governing permissions and limitations under the License. +// This file has been taken from https://github.com/pulp-platform/apb_uart_sv +// and modified by Andrei Solodovnikov in order to be used in +// Architectures of Processor Systems (APS) lab work project + +// Changelog: +// some of the input signals has been hardcoded to constant values +// cfg_div_i input has been replaced by baudrate_i input signal. +// The signal cfg_div_i is now controled by baudrate_i input, and this control +// logic is work from assumption that clk_i is 10 MHz. + module uart_rx ( input logic clk_i, input logic rst_i, diff --git a/Labs/13. Peripheral units/peripheral modules/uart_tx.sv b/Labs/13. Peripheral units/peripheral modules/uart_tx.sv index 90df018..11bbf34 100644 --- a/Labs/13. Peripheral units/peripheral modules/uart_tx.sv +++ b/Labs/13. Peripheral units/peripheral modules/uart_tx.sv @@ -8,6 +8,16 @@ // CONDITIONS OF ANY KIND, either express or implied. See the License for the // specific language governing permissions and limitations under the License. +// This file has been taken from https://github.com/pulp-platform/apb_uart_sv +// and modified by Andrei Solodovnikov in order to be used in +// Architectures of Processor Systems (APS) lab work project + +// Changelog: +// some of the input signals has been hardcoded to constant values +// cfg_div_i input has been replaced by baudrate_i input signal. +// The signal cfg_div_i is now controled by baudrate_i input, and this control +// logic is work from assumption that clk_i is 10 MHz. + module uart_tx ( input logic clk_i, input logic rst_i, diff --git a/Labs/13. Peripheral units/peripheral modules/vgachargen.sv b/Labs/13. Peripheral units/peripheral modules/vgachargen.sv index 0fa22b3..09de262 100644 --- a/Labs/13. Peripheral units/peripheral modules/vgachargen.sv +++ b/Labs/13. Peripheral units/peripheral modules/vgachargen.sv @@ -1,3 +1,13 @@ +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Alexander Kharlamov +* Email(s) : sasha_xarlamov@org.miet.ru + +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ module vgachargen import vgachargen_pkg::*; #( diff --git a/Labs/13. Peripheral units/peripheral modules/vgachargen_pkg.sv b/Labs/13. Peripheral units/peripheral modules/vgachargen_pkg.sv index 5764446..ed7ec72 100644 --- a/Labs/13. Peripheral units/peripheral modules/vgachargen_pkg.sv +++ b/Labs/13. Peripheral units/peripheral modules/vgachargen_pkg.sv @@ -1,3 +1,13 @@ +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Alexander Kharlamov +* Email(s) : sasha_xarlamov@org.miet.ru + +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ package vgachargen_pkg; parameter int unsigned HD = 640; // Display area diff --git a/Labs/13. Peripheral units/sys_clk_rst_gen.sv b/Labs/13. Peripheral units/sys_clk_rst_gen.sv index 06bf8f7..8300824 100644 --- a/Labs/13. Peripheral units/sys_clk_rst_gen.sv +++ b/Labs/13. Peripheral units/sys_clk_rst_gen.sv @@ -1,3 +1,13 @@ +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Andrei Solodovnikov +* Email(s) : hepoh@org.miet.ru + +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ module sys_clk_rst_gen#( parameter DIV_WIDTH = 4 )( diff --git a/Labs/13. Peripheral units/tb_riscv_unit.sv b/Labs/13. Peripheral units/tb_riscv_unit.sv index 83a1344..8057416 100644 --- a/Labs/13. Peripheral units/tb_riscv_unit.sv +++ b/Labs/13. Peripheral units/tb_riscv_unit.sv @@ -1,14 +1,13 @@ -////////////////////////////////////////////////////////////////////////////////// -// Company: MIET -// Engineer: Andrei Solodovnikov - -// Module Name: tb_riscv_unit -// Project Name: RISCV_practicum -// Target Devices: Nexys A7-100T -// Description: tb for peripheral units -// -////////////////////////////////////////////////////////////////////////////////// +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Andrei Solodovnikov +* Email(s) : hepoh@org.miet.ru +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ module tb_riscv_unit(); logic clk; diff --git a/Labs/14. Programming/linker_script.ld b/Labs/14. Programming/linker_script.ld index 139afe0..ad3328f 100644 --- a/Labs/14. Programming/linker_script.ld +++ b/Labs/14. Programming/linker_script.ld @@ -1,3 +1,13 @@ +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Andrei Solodovnikov +* Email(s) : hepoh@org.miet.ru + +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ OUTPUT_FORMAT("elf32-littleriscv") /* Указываем порядок следования байт */ ENTRY(_start) /* мы сообщаем компоновщику, что первая diff --git a/Labs/14. Programming/platform.h b/Labs/14. Programming/platform.h index 3b44e6a..e3f0cd9 100644 --- a/Labs/14. Programming/platform.h +++ b/Labs/14. Programming/platform.h @@ -1,3 +1,13 @@ +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Andrei Solodovnikov +* Email(s) : hepoh@org.miet.ru + +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ #pragma once #include diff --git a/Labs/14. Programming/startup.S b/Labs/14. Programming/startup.S index e87be4b..98dc8e2 100644 --- a/Labs/14. Programming/startup.S +++ b/Labs/14. Programming/startup.S @@ -1,3 +1,13 @@ +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Andrei Solodovnikov +* Email(s) : hepoh@org.miet.ru + +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ .section .boot .global _start diff --git a/Labs/15. Programming device/flash.py b/Labs/15. Programming device/flash.py index 40ff3bb..41c1901 100644 --- a/Labs/15. Programming device/flash.py +++ b/Labs/15. Programming device/flash.py @@ -1,3 +1,13 @@ +# ----------------------------------------------------------------------------- +# Project Name : Architectures of Processor Systems (APS) lab work +# Organization : National Research University of Electronic Technology (MIET) +# Department : Institute of Microdevices and Control Systems +# Author(s) : Andrei Solodovnikov +# Email(s) : hepoh@org.miet.ru +# +# See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +# ------------------------------------------------------------------------------ +# import argparse import serial diff --git a/Labs/15. Programming device/tb_bluster.sv b/Labs/15. Programming device/tb_bluster.sv index 72e8f12..bc8f769 100644 --- a/Labs/15. Programming device/tb_bluster.sv +++ b/Labs/15. Programming device/tb_bluster.sv @@ -1,14 +1,13 @@ -////////////////////////////////////////////////////////////////////////////////// -// Company: MIET -// Engineer: Solodovnikov Andrei - -// Module Name: tb_blaster -// Project Name: RISCV_practicum -// Target Devices: Nexys A7-100T -// Description: tb for programming device -// -////////////////////////////////////////////////////////////////////////////////// +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Andrei Solodovnikov +* Email(s) : hepoh@org.miet.ru +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ module tb_blaster(); logic clk_i; diff --git a/Labs/15. Programming device/tb_top_asic.sv b/Labs/15. Programming device/tb_top_asic.sv index 46a7d85..a377ad9 100644 --- a/Labs/15. Programming device/tb_top_asic.sv +++ b/Labs/15. Programming device/tb_top_asic.sv @@ -1,14 +1,13 @@ -////////////////////////////////////////////////////////////////////////////////// -// Company: MIET -// Engineer: Solodovnikov Andrei - -// Module Name: tb_top_asic -// Project Name: RISCV_practicum -// Target Devices: Nexys A7-100T -// Description: tb for top level entity -// -////////////////////////////////////////////////////////////////////////////////// +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Andrei Solodovnikov +* Email(s) : hepoh@org.miet.ru +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ module tb_top_asic(); logic clk10mhz_i; diff --git a/Labs/16. Coremark/Makefile b/Labs/16. Coremark/Makefile index c49e385..cc6ba17 100644 --- a/Labs/16. Coremark/Makefile +++ b/Labs/16. Coremark/Makefile @@ -1,3 +1,13 @@ +# ----------------------------------------------------------------------------- +# Project Name : Architectures of Processor Systems (APS) lab work +# Organization : National Research University of Electronic Technology (MIET) +# Department : Institute of Microdevices and Control Systems +# Author(s) : Andrei Solodovnikov +# Email(s) : hepoh@org.miet.ru +# +# See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +# ------------------------------------------------------------------------------ +# CC_PATH = /c/riscv_cc/bin CC_PREFIX = riscv-none-elf diff --git a/Labs/16. Coremark/linker_script.ld b/Labs/16. Coremark/linker_script.ld index 47f56a2..4823b42 100644 --- a/Labs/16. Coremark/linker_script.ld +++ b/Labs/16. Coremark/linker_script.ld @@ -1,3 +1,13 @@ +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Andrei Solodovnikov +* Email(s) : hepoh@org.miet.ru + +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ OUTPUT_FORMAT("elf32-littleriscv") /* Указываем порядок следования байт */ ENTRY(_start) /* мы сообщаем компоновщику, что первая diff --git a/Labs/16. Coremark/startup.S b/Labs/16. Coremark/startup.S index 74f5509..cee620a 100644 --- a/Labs/16. Coremark/startup.S +++ b/Labs/16. Coremark/startup.S @@ -1,3 +1,13 @@ +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Andrei Solodovnikov +* Email(s) : hepoh@org.miet.ru + +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ .section .boot .global _start diff --git a/Labs/16. Coremark/tb_coremark.sv b/Labs/16. Coremark/tb_coremark.sv index 0b494f1..8dbd37d 100644 --- a/Labs/16. Coremark/tb_coremark.sv +++ b/Labs/16. Coremark/tb_coremark.sv @@ -1,14 +1,13 @@ -////////////////////////////////////////////////////////////////////////////////// -// Company: MIET -// Engineer: Solodovnikov Andrei - -// Module Name: tb_coremark -// Project Name: RISCV_practicum -// Target Devices: Nexys A7-100T -// Description: tb for running Coremark -// -////////////////////////////////////////////////////////////////////////////////// +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Andrei Solodovnikov +* Email(s) : hepoh@org.miet.ru +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ module tb_coremark(); logic clk10mhz_i; diff --git a/Labs/16. Coremark/tb_timer.sv b/Labs/16. Coremark/tb_timer.sv index 03f6fbe..d4590b6 100644 --- a/Labs/16. Coremark/tb_timer.sv +++ b/Labs/16. Coremark/tb_timer.sv @@ -1,14 +1,13 @@ -////////////////////////////////////////////////////////////////////////////////// -// Company: MIET -// Engineer: Solodovnikov Andrei - -// Module Name: tb_timer -// Project Name: RISCV_practicum -// Target Devices: Nexys A7-100T -// Description: tb for timer -// -////////////////////////////////////////////////////////////////////////////////// +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Andrei Solodovnikov +* Email(s) : hepoh@org.miet.ru +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ module tb_timer(); logic clk_i; diff --git a/Labs/Made-up modules/lab_01.fulladder32.sv b/Labs/Made-up modules/lab_01.fulladder32.sv index f715cf3..6550666 100644 --- a/Labs/Made-up modules/lab_01.fulladder32.sv +++ b/Labs/Made-up modules/lab_01.fulladder32.sv @@ -1,3 +1,13 @@ +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Andrei Solodovnikov +* Email(s) : hepoh@org.miet.ru + +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ module fulladder32( input logic [31:0] a_i, input logic [31:0] b_i, diff --git a/Labs/Made-up modules/lab_03.data_mem.sv b/Labs/Made-up modules/lab_03.data_mem.sv index 732f06a..45829d5 100644 --- a/Labs/Made-up modules/lab_03.data_mem.sv +++ b/Labs/Made-up modules/lab_03.data_mem.sv @@ -1,3 +1,13 @@ +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Nikita Bulavin +* Email(s) : nekkit6@edu.miet.ru + +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ module data_mem ( input logic clk_i, input logic [31:0] addr_i, diff --git a/Labs/Made-up modules/lab_03.instr_mem.sv b/Labs/Made-up modules/lab_03.instr_mem.sv index f878b3e..ebec8e6 100644 --- a/Labs/Made-up modules/lab_03.instr_mem.sv +++ b/Labs/Made-up modules/lab_03.instr_mem.sv @@ -1,3 +1,13 @@ +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Nikita Bulavin +* Email(s) : nekkit6@edu.miet.ru + +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ module instr_mem( input logic [31:0] addr_i, output logic [31:0] read_data_o diff --git a/Labs/Made-up modules/lab_03.register_file.sv b/Labs/Made-up modules/lab_03.register_file.sv index 877e150..0113571 100644 --- a/Labs/Made-up modules/lab_03.register_file.sv +++ b/Labs/Made-up modules/lab_03.register_file.sv @@ -1,3 +1,13 @@ +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Nikita Bulavin +* Email(s) : nekkit6@edu.miet.ru + +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ module rf_riscv( input logic clk_i, input logic write_enable_i, diff --git a/Labs/Made-up modules/lab_05.decoder.sv b/Labs/Made-up modules/lab_05.decoder.sv index de2b932..c7176aa 100644 --- a/Labs/Made-up modules/lab_05.decoder.sv +++ b/Labs/Made-up modules/lab_05.decoder.sv @@ -1,13 +1,13 @@ -////////////////////////////////////////////////////////////////////////////////// -// Company: MIET -// Engineer: Alexey Kozin - -// Module Name: decoder_riscv -// Project Name: RISCV_practicum -// Target Devices: Nexys A7-100T -// Description: main decoder for risc-v processor -////////////////////////////////////////////////////////////////////////////////// +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Alexey Kozin +* Email(s) : @edu.miet.ru +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ module gpr_we_table (gis_ew_rpg, edocpo_6, edocpo_5, edocpo_4, edocpo_3, edocpo_2); output logic gis_ew_rpg; input edocpo_6, edocpo_5, edocpo_4, edocpo_3, edocpo_2; diff --git a/Labs/Made-up modules/lab_07.ext_mem.sv b/Labs/Made-up modules/lab_07.ext_mem.sv index b31e17c..4483464 100644 --- a/Labs/Made-up modules/lab_07.ext_mem.sv +++ b/Labs/Made-up modules/lab_07.ext_mem.sv @@ -1,13 +1,13 @@ -////////////////////////////////////////////////////////////////////////////////// -// Company: MIET -// Engineer: Andrei Solodovnikov +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Andrei Solodovnikov +* Email(s) : hepoh@org.miet.ru -// Module Name: ext_mem -// Project Name: RISCV_practicum -// Target Devices: Nexys A7-100T -// Description: external memory with byte_enable support -// -////////////////////////////////////////////////////////////////////////////////// +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ module ext_mem( input logic clk_i, input logic mem_req_i, diff --git a/Labs/Made-up modules/lab_08.lsu.sv b/Labs/Made-up modules/lab_08.lsu.sv index 3853281..89401a4 100644 --- a/Labs/Made-up modules/lab_08.lsu.sv +++ b/Labs/Made-up modules/lab_08.lsu.sv @@ -1,13 +1,13 @@ -////////////////////////////////////////////////////////////////////////////////// -// Company: MIET -// Engineer: Andrei Solodovnikov +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Andrei Solodovnikov +* Email(s) : hepoh@org.miet.ru -// Module Name: lsu_testbench -// Project Name: RISCV_practicum -// Target Devices: Nexys A7-100T -// Description: Load&Store Unit -// -////////////////////////////////////////////////////////////////////////////////// +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ module riscv_lsu( input logic clk_i, input logic rst_i, diff --git a/Labs/Made-up modules/lab_10.csr.sv b/Labs/Made-up modules/lab_10.csr.sv index 7c8466d..f6b5f3f 100644 --- a/Labs/Made-up modules/lab_10.csr.sv +++ b/Labs/Made-up modules/lab_10.csr.sv @@ -1,3 +1,13 @@ +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Andrei Solodovnikov +* Email(s) : hepoh@org.miet.ru + +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ module csr_controller ( input logic clk_i, @@ -58,14 +68,14 @@ module csr_controller ( assign ljljlj = rs1_data_i; always_comb begin case (llafdh[2:0]) - 0: abvD3l <= ljljlj ^ rs1_data_i; - 1: abvD3l <= ljljlj; - 2: abvD3l <= ljljlj | ljiufdqwq; - 3: abvD3l <= ~ljljlj & ljiufdqwq; - 4: abvD3l <= ~rs1_data_i ^ ~ljljlj; - 5: abvD3l <= ljiuasdf; - 6: abvD3l <= ljiuasdf | ljiufdqwq; - 7: abvD3l <= ~ljiuasdf & ljiufdqwq; + 0: abvD3l = ljljlj ^ rs1_data_i; + 1: abvD3l = ljljlj; + 2: abvD3l = ljljlj | ljiufdqwq; + 3: abvD3l = ~ljljlj & ljiufdqwq; + 4: abvD3l = ~rs1_data_i ^ ~ljljlj; + 5: abvD3l = ljiuasdf; + 6: abvD3l = ljiuasdf | ljiufdqwq; + 7: abvD3l = ~ljiuasdf & ljiufdqwq; endcase end diff --git a/Labs/Made-up modules/lab_10.irq.sv b/Labs/Made-up modules/lab_10.irq.sv index 9abf80f..46f7f3e 100644 --- a/Labs/Made-up modules/lab_10.irq.sv +++ b/Labs/Made-up modules/lab_10.irq.sv @@ -1,3 +1,13 @@ +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Andrei Solodovnikov +* Email(s) : hepoh@org.miet.ru + +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ module interrupt_controller( input logic clk_i, input logic rst_i, diff --git a/Other/vector_abs/half_divider.sv b/Other/vector_abs/half_divider.sv index 1e4731b..4d3e03b 100644 --- a/Other/vector_abs/half_divider.sv +++ b/Other/vector_abs/half_divider.sv @@ -1,3 +1,13 @@ +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Andrei Solodovnikov +* Email(s) : hepoh@org.miet.ru + +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ module half_divider( input logic [31:0] numerator, output logic [31:0] quotient diff --git a/Other/vector_abs/max_min.sv b/Other/vector_abs/max_min.sv index 457e8eb..5d29f88 100644 --- a/Other/vector_abs/max_min.sv +++ b/Other/vector_abs/max_min.sv @@ -1,3 +1,13 @@ +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Andrei Solodovnikov +* Email(s) : hepoh@org.miet.ru + +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ module max_min( input logic [31:0] a, input logic [31:0] b, diff --git a/Other/vector_abs/tb_vector_abs.sv b/Other/vector_abs/tb_vector_abs.sv index fcebb01..467c51e 100644 --- a/Other/vector_abs/tb_vector_abs.sv +++ b/Other/vector_abs/tb_vector_abs.sv @@ -1,3 +1,13 @@ +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Andrei Solodovnikov +* Email(s) : hepoh@org.miet.ru + +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ module tb_vector_abs(); logic [31:0] a; diff --git a/Other/vector_abs/vector_abs.sv b/Other/vector_abs/vector_abs.sv index a89e9e7..8f77d88 100644 --- a/Other/vector_abs/vector_abs.sv +++ b/Other/vector_abs/vector_abs.sv @@ -1,3 +1,13 @@ +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Andrei Solodovnikov +* Email(s) : hepoh@org.miet.ru + +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ module vector_abs( input logic [31:0] x, input logic [31:0] y,