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111 lines
3.4 KiB
Systemverilog
111 lines
3.4 KiB
Systemverilog
/* -----------------------------------------------------------------------------
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* Project Name : Architectures of Processor Systems (APS) lab work
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* Organization : National Research University of Electronic Technology (MIET)
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* Department : Institute of Microdevices and Control Systems
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* Author(s) : Nikita Bulavin
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* Email(s) : nekkit6@edu.miet.ru
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See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
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* ------------------------------------------------------------------------------
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*/
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module tb_data_mem();
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parameter ADDR_SIZE = 16384;
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parameter TIME_OPERATION = 20;
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parameter STEP = 8;
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logic CLK;
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logic REQ;
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logic WE;
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logic [31:0] A;
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logic [31:0] WD;
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logic [31:0] RD;
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data_mem DUT (
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.clk_i (CLK),
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.mem_req_i (REQ),
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.write_enable_i (WE ),
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.addr_i (A ),
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.write_data_i (WD),
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.read_data_o (RD)
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);
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logic [31:0] RDa;
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integer i, hash, err_count = 0;
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assign A = i;
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parameter CLK_FREQ_MHz = 100;
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parameter CLK_SEMI_PERIOD= 1e3/CLK_FREQ_MHz/2;
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initial CLK <= 0;
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always #CLK_SEMI_PERIOD CLK = ~CLK;
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initial begin
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$timeformat(-9, 2, " ns", 3);
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$display( "\nStart test: \n\n==========================\nCLICK THE BUTTON 'Run All'\n==========================\n"); $stop();
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REQ = 1;
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WE = 0;
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@(posedge CLK);
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for (i = 0; i < ADDR_SIZE; i = i + STEP) begin
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hash = (i+4)*8/15*16/23*42;
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WE = 1;
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WD = hash;
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@(posedge CLK)#3;
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end
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WE = 0;
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@(posedge CLK);
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for (i = 0; i < ADDR_SIZE; i = i + STEP) begin
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@(posedge CLK)#3;
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hash = (i+4)*8/15*16/23*42;
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if(RD !== hash) begin
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$error("Read data: %0h is unequal written data: %0h at addres: %0h, time: %t", RD, hash, i, $time);
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err_count = err_count + 1;
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end
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end
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for (i = 0; i < (ADDR_SIZE+STEP); i = i + 1 + $urandom() % STEP) begin
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REQ = |($urandom %10);
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WE = 0;
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#TIME_OPERATION;
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RDa = RD;
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WD = $urandom;
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#TIME_OPERATION;
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WE = $urandom % 2;
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#TIME_OPERATION;
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if ((!WE && REQ) && RD !== RDa) begin
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$error("When reading (write_enable_i = %h), the data %h is overwritten with data %h at address %h, time: %t", WE, RDa, RD, A, $time);
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err_count = err_count + 1;
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end
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#TIME_OPERATION;
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end
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#TIME_OPERATION;
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REQ = 1;
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WE = 0;
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#TIME_OPERATION;
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for (i = 0; i < 4; i = i + 1) begin
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if(i==0) begin
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repeat(2)@(posedge CLK);
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#1; RDa = RD;
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end else
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if(RD !== RDa) begin
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$error("incorrect conversion of the reading address = %h, time: %t", A, $time);
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err_count = err_count + 1;
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end
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#TIME_OPERATION;
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end
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i = 0; WE = 0; REQ = 1;
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@(posedge CLK);
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@(negedge CLK);
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i = 4;
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#1; RDa = RD;
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@(posedge CLK); #1;
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if (RD == RDa) begin
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$error("reading from data memory must be synchronous, time: %t", $time);
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err_count = err_count + 1;
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end
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@(posedge CLK);
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$display("Number of errors: %d", err_count);
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if( !err_count ) $display("\ndata_mem SUCCESS!!!\n");
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$finish();
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end
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endmodule
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