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93 lines
3.2 KiB
Systemverilog
93 lines
3.2 KiB
Systemverilog
/* -----------------------------------------------------------------------------
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* Project Name : Architectures of Processor Systems (APS) lab work
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* Organization : National Research University of Electronic Technology (MIET)
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* Department : Institute of Microdevices and Control Systems
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* Author(s) : Nikita Bulavin
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* Email(s) : nekkit6@edu.miet.ru
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See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
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* ------------------------------------------------------------------------------
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*/
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module nexys_CYBERcobra_dz(
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input CLK100,
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input resetn,
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input BTND,
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input [15:0] SW,
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output CA, CB, CC, CD, CE, CF, CG,
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output [7:0] AN
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);
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CYBERcobra dut(
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.clk_i(btn),
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.rst_i(!resetn),
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.sw_i(SW[15:0]),
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.out_o(out)
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);
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localparam pwm = 1000;
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reg [9:0] counter;
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reg [3:0] semseg;
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reg [7:0] ANreg;
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reg CAr, CBr, CCr, CDr, CEr, CFr, CGr;
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reg btn;
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wire [31:0] out;
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assign AN[7:0] = ANreg[7:0];
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assign {CA, CB, CC, CD, CE, CF, CG} = {CAr, CBr, CCr, CDr, CEr, CFr, CGr};
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always @(posedge CLK100) begin
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if (!resetn) begin
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counter <= 'b0;
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ANreg[7:0] <= 8'b11111111;
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{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1111111;
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btn <= BTND;
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end
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else begin
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btn <= BTND;
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if (counter < pwm) counter = counter + 'b1;
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else begin
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counter = 'b0;
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ANreg[1] <= ANreg[0];
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ANreg[2] <= ANreg[1];
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ANreg[3] <= ANreg[2];
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ANreg[4] <= ANreg[3];
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ANreg[5] <= ANreg[4];
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ANreg[6] <= ANreg[5];
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ANreg[7] <= ANreg[6];
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ANreg[0] <= !(ANreg[6:0] == 7'b1111111);
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end
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case (1'b0)
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ANreg[0]: semseg <= out[3 : 0];
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ANreg[1]: semseg <= out[7 : 4];
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ANreg[2]: semseg <= out[11: 8];
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ANreg[3]: semseg <= out[15:12];
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ANreg[4]: semseg <= out[19:16];
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ANreg[5]: semseg <= out[23:20];
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ANreg[6]: semseg <= out[27:24];
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ANreg[7]: semseg <= out[31:28];
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endcase
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case (semseg)
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4'h0: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0000001;
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4'h1: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1001111;
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4'h2: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0010010;
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4'h3: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0000110;
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4'h4: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1001100;
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4'h5: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0100100;
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4'h6: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0100000;
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4'h7: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0001111;
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4'h8: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0000000;
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4'h9: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0000100;
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4'hA: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0001000;
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4'hB: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1100000;
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4'hC: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0110001;
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4'hD: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1000010;
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4'hE: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0110000;
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4'hF: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0111000;
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default: {CAr,CBr,CCr,CDr, CEr, CFr, CGr} <= 7'b0111111;
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endcase
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end
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end
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endmodule
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