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https://github.com/MPSU/APS.git
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143 lines
4.1 KiB
Systemverilog
143 lines
4.1 KiB
Systemverilog
/* -----------------------------------------------------------------------------
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* Project Name : Architectures of Processor Systems (APS) lab work
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* Organization : National Research University of Electronic Technology (MIET)
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* Department : Institute of Microdevices and Control Systems
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* Author(s) : Andrei Solodovnikov
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* Email(s) : hepoh@org.miet.ru
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See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
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* ------------------------------------------------------------------------------
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*/
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module tb_coremark();
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logic clk10mhz_i;
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logic aresetn_i;
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logic rx_i;
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logic tx_o;
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logic clk_i;
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logic rst_i;
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assign aresetn_i = !rst_i;
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assign clk10mhz_i = clk_i;
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logic rx_busy, rx_valid, tx_busy, tx_valid;
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logic [7:0] rx_data, tx_data;
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always #50ns clk_i = !clk_i;
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byte coremark_msg[103];
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integer coremark_cntr;
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initial begin
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$timeformat(-9, 2, " ns", 3);
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clk_i = 0;
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rst_i <= 0;
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@(posedge clk_i);
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rst_i <= 1;
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repeat(2) @(posedge clk_i);
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rst_i <= 0;
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dummy_programming();
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coremark_cntr = 0;
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coremark_msg = {32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32};
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forever begin
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@(posedge clk_i);
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if(rx_valid) begin
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if((rx_data == 10) | (rx_data == 13)) begin
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$display("%s", coremark_msg);
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coremark_cntr = 0;
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coremark_msg = {32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32};
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end
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else begin
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coremark_msg[coremark_cntr] = rx_data;
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coremark_cntr++;
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end
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end
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end
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end
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initial #500ms $finish();
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riscv_top_asic DUT(.clk10mhz_i, .aresetn_i, .rx_i, .tx_o);
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uart_rx rx(
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.clk_i (clk_i ),
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.rst_i (rst_i ),
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.rx_i (tx_o ),
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.busy_o (rx_busy ),
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.baudrate_i (17'd115200 ),
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.parity_en_i(1'b1 ),
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.stopbit_i (1'b1 ),
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.rx_data_o (rx_data ),
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.rx_valid_o (rx_valid )
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);
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uart_tx tx(
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.clk_i (clk_i ),
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.rst_i (rst_i ),
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.tx_o (rx_i ),
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.busy_o (tx_busy ),
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.baudrate_i (17'd115200 ),
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.parity_en_i(1'b1 ),
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.stopbit_i (1'b1 ),
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.tx_data_i (tx_data ),
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.tx_valid_i (tx_valid )
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);
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task send_data(input byte mem[$]);
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for(int i = mem.size()-1; i >=0; i--) begin
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tx_data = mem[i];
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tx_valid = 1'b1;
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@(posedge clk_i);
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tx_valid = 1'b0;
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@(posedge clk_i);
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while(tx_busy) @(posedge clk_i);
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end
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endtask
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task rcv_data(input int size);
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byte str[57];
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logic [3:0][7:0] size_val;
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for(int i = 0; i < size; i++) begin
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@(posedge clk_i);
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while(!rx_valid)@(posedge clk_i);
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str[i] = rx_data;
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size_val[3-i] = rx_data;
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end
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if(size!=4)$display("%s", str);
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else $display("%d", size_val);
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wait(tx_o);
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endtask
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task program_region(input byte mem[$], input logic [3:0][7:0] start_addr);
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byte str [4];
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logic [3:0][7:0] size;
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size = mem.size();
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if(start_addr) begin
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str = {start_addr[0],start_addr[1],start_addr[2],start_addr[3]};
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send_data(str);
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end
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rcv_data(40);
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str = {size[0],size[1],size[2],size[3]};
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send_data(str);
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rcv_data(4);
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send_data(mem);
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rcv_data(57);
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endtask
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task finish_programming();
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send_data({8'd0, 8'd0, 8'd0, 8'd0});
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endtask
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task dummy_programming();
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byte str [4] = {8'd0, 8'd0, 8'd0, 8'd0};
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rcv_data(40);
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send_data(str);
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rcv_data(4);
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rcv_data(57);
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send_data(str);
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endtask
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endmodule
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