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Удаление неинформативных строк из шапки модуля с комментариями

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This commit is contained in:
Andrei Solodovnikov
2023-11-15 14:34:03 +03:00
parent 4be66525d6
commit 1b4f666e25
13 changed files with 31 additions and 163 deletions
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12
Labs/01. Adder/tb_fulladder.sv
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@@ -1,21 +1,11 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Nikita Bulavin
//
// Create Date:
// Design Name:
// Module Name: tb_fulladder
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Tool Versions:
// Description: tb for 1-bit fulladder
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tb_fulladder();

12
Labs/01. Adder/tb_fulladder32.sv
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@@ -1,21 +1,11 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Nikita Bulavin
//
// Create Date:
// Design Name:
// Module Name: tb_fulladder32
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Tool Versions:
// Description: tb for 32-bit fulladder
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tb_fulladder32();

12
Labs/01. Adder/tb_fulladder4.sv
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@@ -1,21 +1,11 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Nikita Bulavin
//
// Create Date:
// Design Name:
// Module Name: tb_fulladder4
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Tool Versions:
// Description: tb for 4-bit fulladder
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tb_fulladder4();

12
Labs/02. Arithmetic-logic unit/tb_miriscv_alu.sv
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@@ -1,21 +1,11 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Nikita Bulavin
//
// Create Date:
// Design Name:
// Module Name: tb_miriscv_alu
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Tool Versions:
// Description: tb for miriscv alu
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tb_miriscv_alu();

12
Labs/03. Register file and memory/tb_data_mem.sv
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@@ -1,21 +1,11 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Nikita Bulavin
//
// Create Date:
// Design Name:
// Module Name: tb_data_mem
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Tool Versions:
// Description: tb for data memory
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tb_data_mem();

47
Labs/03. Register file and memory/tb_instr_mem.sv
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@@ -1,21 +1,11 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Nikita Bulavin
//
// Create Date:
// Design Name:
// Module Name: tb_instr_mem
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Tool Versions:
// Description: tb for instruction memory
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tb_instr_mem();
@@ -23,25 +13,25 @@ module tb_instr_mem();
parameter ADDR_SIZE = 4096;
parameter TIME_OPERATION = 10;
parameter STEP = 8;
logic [31:0] addr;
logic [31:0] RD;
logic [31:0] RDref;
instr_mem_ref DUTref(
.addr_i(addr),
.read_data_o(RDref)
);
instr_mem DUT (
.addr_i(addr),
.read_data_o(RD)
);
integer i, err_count = 0;
assign addr = i;
initial begin
$timeformat (-9, 2, "ns");
$display( "\nStart test: \n\n==========================\nCLICK THE BUTTON 'Run All'\n==========================\n"); $stop();
@@ -56,7 +46,7 @@ parameter STEP = 8;
if( !err_count ) $display("\n instr_mem SUCCESS!!!\n");
$finish();
end
endmodule
module instr_mem_ref(
@@ -73,18 +63,13 @@ reg [31:0] RAM [0:1023];
initial $readmemh("program.txt", RAM);
always_comb begin
case(addr_i > {12{1'b1}})
0: begin
read_data_o['h1f:'h1c]=RAM[{2'b00, addr_i[{5{1'b1}}:2]}][{5{1'b1}}:{3'd7,2'b00}];
read_data_o[42-23-:`asdasdhkjasdsa]=RAM[{2'b00, addr_i[{5{1'b1}}:2]}][19:{1'b1,4'h0}];
read_data_o[`akjsdnnaskjdn-:`asdasdhkjasdsa]=RAM[{2'b00, addr_i[{5{1'b1}}:2]}][{3{1'b1}}:{1'b1,2'h0}];
read_data_o[42-19-:`asdasdhkjasdsa]=RAM[{2'b00, addr_i[{5{1'b1}}:2]}][23:{{2{2'b10}},1'b0}];
read_data_o['h1b:'h18]=RAM[{2'b00, addr_i[{5{1'b1}}:2]}][27:{2'b11,3'b000}];
read_data_o[`akjsdnnaskjdn+`asdasdhkjasdsa:(`akjsdnnaskjdn+`asdasdhkjasdsa)-`cdyfguvhbjnmk]=RAM[{2'b00, addr_i[{5{1'b1}}:2]}][11:8];
read_data_o[`akjsdnnaskjdn-`asdasdhkjasdsa-:`asdasdhkjasdsa]=RAM[{2'b00, addr_i[{5{1'b1}}:2]}][3:0];
read_data_o[(`akjsdnnaskjdn<<(`asdasdhkjasdsa-`cdyfguvhbjnmk)) + (`asdasdhkjasdsa-`cdyfguvhbjnmk):12 ]=RAM[{2'b00, addr_i[{5{1'b1}}:2]}][{4{1'b1}}:12];
end
default: read_data_o = 'hBA & 'h45;
endcase
read_data_o['h1f:'h1c]=RAM[{2'b00, addr_i[5'd28^5'o27:2]}][{5{1'b1}}:{3'd7,2'b00}];
read_data_o[42-23-:`asdasdhkjasdsa]=RAM[{2'b00, addr_i[5'h1C-5'd17:2]}][19:{1'b1,4'h0}];
read_data_o[`akjsdnnaskjdn-:`asdasdhkjasdsa]=RAM[{2'b00, addr_i[5'd28^5'o27:2]}][{3{1'b1}}:{1'b1,2'h0}];
read_data_o[42-19-:`asdasdhkjasdsa]=RAM[{2'b00, addr_i[5'h1C-5'd17:2]}][23:{{2{2'b10}},1'b0}];
read_data_o['h1b:'h18]=RAM[{2'b00, addr_i[5'h1C-5'd17:2]}][27:{2'b11,3'b000}];
read_data_o[`akjsdnnaskjdn+`asdasdhkjasdsa:(`akjsdnnaskjdn+`asdasdhkjasdsa)-`cdyfguvhbjnmk]=RAM[{2'b00, addr_i[5'h1C-5'd17:2]}][11:8];
read_data_o[`akjsdnnaskjdn-`asdasdhkjasdsa-:`asdasdhkjasdsa]=RAM[{2'b00, addr_i[5'd28^5'o27:2]}][3:0];
read_data_o[(`akjsdnnaskjdn<<(`asdasdhkjasdsa-`cdyfguvhbjnmk)) + (`asdasdhkjasdsa-`cdyfguvhbjnmk):12 ]=RAM[{2'b00, addr_i[5'h1C-5'd17:2]}][{4{1'b1}}:12];
end
endmodule

12
Labs/03. Register file and memory/tb_rf_riscv.sv
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@@ -1,21 +1,11 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Nikita Bulavin
//
// Create Date:
// Design Name:
// Module Name: tb_rf_riscv
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Tool Versions:
// Description: tb for RISC-V register file
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tb_rf_riscv();

12
Labs/04. Primitive programmable device/tb_cybercobra.sv
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@@ -1,21 +1,11 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Nikita Bulavin
//
// Create Date:
// Design Name:
// Module Name: tb_cybercobra
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Tool Versions:
// Description: tb for CYBERcobra 3000 Pro 2.1
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tb_CYBERcobra();

13
Labs/05. Main decoder/tb_decoder_riscv.sv
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@@ -1,21 +1,12 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Nikita Bulavin
//
// Create Date:
// Design Name:
// Module Name: tb_decoder_riscv
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Tool Versions:
// Description: tb for decoder riscv
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tb_decoder_riscv();

12
Labs/06. Datapath/tb_riscv_unit.sv
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@@ -1,21 +1,11 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Nikita Bulavin
//
// Create Date:
// Design Name:
// Module Name: tb_riscv_unit
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Tool Versions:
// Description: tb for datapath
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tb_riscv_unit();

13
Labs/11. Interrupt integration/tb_irq_unit.sv
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@@ -1,21 +1,12 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Andrei Solodovnikov
//
// Create Date:
// Design Name:
// Module Name: tb_riscv_unit
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Tool Versions:
// Description: tb for riscv unit with irq support
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tb_irq_unit();

13
Labs/12. Peripheral units/testbench.sv
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@@ -1,21 +1,12 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Nikita Bulavin
//
// Create Date:
// Design Name:
// Module Name: tb_riscv_unit
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Tool Versions:
// Description: tb for peripheral units
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tb_riscv_unit();

12
Labs/Made-up modules/lab_05.decoder.sv
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@@ -1,21 +1,11 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Alexey Kozin
//
// Create Date: 10/08/2023 07:39:15 AM
// Design Name:
// Module Name: decoder_riscv
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Tool Versions:
// Description: main decoder for risc-v processor
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module gpr_we_table (gis_ew_rpg, edocpo_6, edocpo_5, edocpo_4, edocpo_3, edocpo_2);