From 1b4f666e2514fffd15e75350d92e0466f9d809b9 Mon Sep 17 00:00:00 2001 From: Andrei Solodovnikov Date: Wed, 15 Nov 2023 14:34:03 +0300 Subject: [PATCH] =?UTF-8?q?=D0=A3=D0=B4=D0=B0=D0=BB=D0=B5=D0=BD=D0=B8?= =?UTF-8?q?=D0=B5=20=D0=BD=D0=B5=D0=B8=D0=BD=D1=84=D0=BE=D1=80=D0=BC=D0=B0?= =?UTF-8?q?=D1=82=D0=B8=D0=B2=D0=BD=D1=8B=D1=85=20=D1=81=D1=82=D1=80=D0=BE?= =?UTF-8?q?=D0=BA=20=D0=B8=D0=B7=20=D1=88=D0=B0=D0=BF=D0=BA=D0=B8=20=D0=BC?= =?UTF-8?q?=D0=BE=D0=B4=D1=83=D0=BB=D1=8F=20=D1=81=20=D0=BA=D0=BE=D0=BC?= =?UTF-8?q?=D0=BC=D0=B5=D0=BD=D1=82=D0=B0=D1=80=D0=B8=D1=8F=D0=BC=D0=B8?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Labs/01. Adder/tb_fulladder.sv | 12 +---- Labs/01. Adder/tb_fulladder32.sv | 12 +---- Labs/01. Adder/tb_fulladder4.sv | 12 +---- .../tb_miriscv_alu.sv | 12 +---- .../tb_data_mem.sv | 12 +---- .../tb_instr_mem.sv | 47 +++++++------------ .../tb_rf_riscv.sv | 12 +---- .../tb_cybercobra.sv | 12 +---- Labs/05. Main decoder/tb_decoder_riscv.sv | 13 +---- Labs/06. Datapath/tb_riscv_unit.sv | 12 +---- Labs/11. Interrupt integration/tb_irq_unit.sv | 13 +---- Labs/12. Peripheral units/testbench.sv | 13 +---- Labs/Made-up modules/lab_05.decoder.sv | 12 +---- 13 files changed, 31 insertions(+), 163 deletions(-) diff --git a/Labs/01. Adder/tb_fulladder.sv b/Labs/01. Adder/tb_fulladder.sv index 1804578..2150799 100644 --- a/Labs/01. Adder/tb_fulladder.sv +++ b/Labs/01. Adder/tb_fulladder.sv @@ -1,21 +1,11 @@ ////////////////////////////////////////////////////////////////////////////////// // Company: MIET // Engineer: Nikita Bulavin -// -// Create Date: -// Design Name: + // Module Name: tb_fulladder // Project Name: RISCV_practicum // Target Devices: Nexys A7-100T -// Tool Versions: // Description: tb for 1-bit fulladder -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// ////////////////////////////////////////////////////////////////////////////////// module tb_fulladder(); diff --git a/Labs/01. Adder/tb_fulladder32.sv b/Labs/01. Adder/tb_fulladder32.sv index 152f6b2..5070e6c 100644 --- a/Labs/01. Adder/tb_fulladder32.sv +++ b/Labs/01. Adder/tb_fulladder32.sv @@ -1,21 +1,11 @@ ////////////////////////////////////////////////////////////////////////////////// // Company: MIET // Engineer: Nikita Bulavin -// -// Create Date: -// Design Name: + // Module Name: tb_fulladder32 // Project Name: RISCV_practicum // Target Devices: Nexys A7-100T -// Tool Versions: // Description: tb for 32-bit fulladder -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// ////////////////////////////////////////////////////////////////////////////////// module tb_fulladder32(); diff --git a/Labs/01. Adder/tb_fulladder4.sv b/Labs/01. Adder/tb_fulladder4.sv index 927c360..4c5a9ca 100644 --- a/Labs/01. Adder/tb_fulladder4.sv +++ b/Labs/01. Adder/tb_fulladder4.sv @@ -1,21 +1,11 @@ ////////////////////////////////////////////////////////////////////////////////// // Company: MIET // Engineer: Nikita Bulavin -// -// Create Date: -// Design Name: + // Module Name: tb_fulladder4 // Project Name: RISCV_practicum // Target Devices: Nexys A7-100T -// Tool Versions: // Description: tb for 4-bit fulladder -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// ////////////////////////////////////////////////////////////////////////////////// module tb_fulladder4(); diff --git a/Labs/02. Arithmetic-logic unit/tb_miriscv_alu.sv b/Labs/02. Arithmetic-logic unit/tb_miriscv_alu.sv index e490b32..d42646b 100644 --- a/Labs/02. Arithmetic-logic unit/tb_miriscv_alu.sv +++ b/Labs/02. Arithmetic-logic unit/tb_miriscv_alu.sv @@ -1,21 +1,11 @@ ////////////////////////////////////////////////////////////////////////////////// // Company: MIET // Engineer: Nikita Bulavin -// -// Create Date: -// Design Name: + // Module Name: tb_miriscv_alu // Project Name: RISCV_practicum // Target Devices: Nexys A7-100T -// Tool Versions: // Description: tb for miriscv alu -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// ////////////////////////////////////////////////////////////////////////////////// module tb_miriscv_alu(); diff --git a/Labs/03. Register file and memory/tb_data_mem.sv b/Labs/03. Register file and memory/tb_data_mem.sv index efb7fb3..6430370 100644 --- a/Labs/03. Register file and memory/tb_data_mem.sv +++ b/Labs/03. Register file and memory/tb_data_mem.sv @@ -1,21 +1,11 @@ ////////////////////////////////////////////////////////////////////////////////// // Company: MIET // Engineer: Nikita Bulavin -// -// Create Date: -// Design Name: + // Module Name: tb_data_mem // Project Name: RISCV_practicum // Target Devices: Nexys A7-100T -// Tool Versions: // Description: tb for data memory -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// ////////////////////////////////////////////////////////////////////////////////// module tb_data_mem(); diff --git a/Labs/03. Register file and memory/tb_instr_mem.sv b/Labs/03. Register file and memory/tb_instr_mem.sv index 4297e62..c467f26 100644 --- a/Labs/03. Register file and memory/tb_instr_mem.sv +++ b/Labs/03. Register file and memory/tb_instr_mem.sv @@ -1,21 +1,11 @@ ////////////////////////////////////////////////////////////////////////////////// // Company: MIET // Engineer: Nikita Bulavin -// -// Create Date: -// Design Name: + // Module Name: tb_instr_mem // Project Name: RISCV_practicum // Target Devices: Nexys A7-100T -// Tool Versions: // Description: tb for instruction memory -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// ////////////////////////////////////////////////////////////////////////////////// module tb_instr_mem(); @@ -23,25 +13,25 @@ module tb_instr_mem(); parameter ADDR_SIZE = 4096; parameter TIME_OPERATION = 10; parameter STEP = 8; - + logic [31:0] addr; logic [31:0] RD; logic [31:0] RDref; - + instr_mem_ref DUTref( .addr_i(addr), .read_data_o(RDref) ); - + instr_mem DUT ( .addr_i(addr), .read_data_o(RD) ); - + integer i, err_count = 0; - + assign addr = i; - + initial begin $timeformat (-9, 2, "ns"); $display( "\nStart test: \n\n==========================\nCLICK THE BUTTON 'Run All'\n==========================\n"); $stop(); @@ -56,7 +46,7 @@ parameter STEP = 8; if( !err_count ) $display("\n instr_mem SUCCESS!!!\n"); $finish(); end - + endmodule module instr_mem_ref( @@ -73,18 +63,13 @@ reg [31:0] RAM [0:1023]; initial $readmemh("program.txt", RAM); always_comb begin - case(addr_i > {12{1'b1}}) - 0: begin - read_data_o['h1f:'h1c]=RAM[{2'b00, addr_i[{5{1'b1}}:2]}][{5{1'b1}}:{3'd7,2'b00}]; - read_data_o[42-23-:`asdasdhkjasdsa]=RAM[{2'b00, addr_i[{5{1'b1}}:2]}][19:{1'b1,4'h0}]; - read_data_o[`akjsdnnaskjdn-:`asdasdhkjasdsa]=RAM[{2'b00, addr_i[{5{1'b1}}:2]}][{3{1'b1}}:{1'b1,2'h0}]; - read_data_o[42-19-:`asdasdhkjasdsa]=RAM[{2'b00, addr_i[{5{1'b1}}:2]}][23:{{2{2'b10}},1'b0}]; - read_data_o['h1b:'h18]=RAM[{2'b00, addr_i[{5{1'b1}}:2]}][27:{2'b11,3'b000}]; - read_data_o[`akjsdnnaskjdn+`asdasdhkjasdsa:(`akjsdnnaskjdn+`asdasdhkjasdsa)-`cdyfguvhbjnmk]=RAM[{2'b00, addr_i[{5{1'b1}}:2]}][11:8]; - read_data_o[`akjsdnnaskjdn-`asdasdhkjasdsa-:`asdasdhkjasdsa]=RAM[{2'b00, addr_i[{5{1'b1}}:2]}][3:0]; - read_data_o[(`akjsdnnaskjdn<<(`asdasdhkjasdsa-`cdyfguvhbjnmk)) + (`asdasdhkjasdsa-`cdyfguvhbjnmk):12 ]=RAM[{2'b00, addr_i[{5{1'b1}}:2]}][{4{1'b1}}:12]; - end - default: read_data_o = 'hBA & 'h45; - endcase + read_data_o['h1f:'h1c]=RAM[{2'b00, addr_i[5'd28^5'o27:2]}][{5{1'b1}}:{3'd7,2'b00}]; + read_data_o[42-23-:`asdasdhkjasdsa]=RAM[{2'b00, addr_i[5'h1C-5'd17:2]}][19:{1'b1,4'h0}]; + read_data_o[`akjsdnnaskjdn-:`asdasdhkjasdsa]=RAM[{2'b00, addr_i[5'd28^5'o27:2]}][{3{1'b1}}:{1'b1,2'h0}]; + read_data_o[42-19-:`asdasdhkjasdsa]=RAM[{2'b00, addr_i[5'h1C-5'd17:2]}][23:{{2{2'b10}},1'b0}]; + read_data_o['h1b:'h18]=RAM[{2'b00, addr_i[5'h1C-5'd17:2]}][27:{2'b11,3'b000}]; + read_data_o[`akjsdnnaskjdn+`asdasdhkjasdsa:(`akjsdnnaskjdn+`asdasdhkjasdsa)-`cdyfguvhbjnmk]=RAM[{2'b00, addr_i[5'h1C-5'd17:2]}][11:8]; + read_data_o[`akjsdnnaskjdn-`asdasdhkjasdsa-:`asdasdhkjasdsa]=RAM[{2'b00, addr_i[5'd28^5'o27:2]}][3:0]; + read_data_o[(`akjsdnnaskjdn<<(`asdasdhkjasdsa-`cdyfguvhbjnmk)) + (`asdasdhkjasdsa-`cdyfguvhbjnmk):12 ]=RAM[{2'b00, addr_i[5'h1C-5'd17:2]}][{4{1'b1}}:12]; end endmodule diff --git a/Labs/03. Register file and memory/tb_rf_riscv.sv b/Labs/03. Register file and memory/tb_rf_riscv.sv index 7ec103a..d572f18 100644 --- a/Labs/03. Register file and memory/tb_rf_riscv.sv +++ b/Labs/03. Register file and memory/tb_rf_riscv.sv @@ -1,21 +1,11 @@ ////////////////////////////////////////////////////////////////////////////////// // Company: MIET // Engineer: Nikita Bulavin -// -// Create Date: -// Design Name: + // Module Name: tb_rf_riscv // Project Name: RISCV_practicum // Target Devices: Nexys A7-100T -// Tool Versions: // Description: tb for RISC-V register file -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// ////////////////////////////////////////////////////////////////////////////////// module tb_rf_riscv(); diff --git a/Labs/04. Primitive programmable device/tb_cybercobra.sv b/Labs/04. Primitive programmable device/tb_cybercobra.sv index 12025ea..aa688b0 100644 --- a/Labs/04. Primitive programmable device/tb_cybercobra.sv +++ b/Labs/04. Primitive programmable device/tb_cybercobra.sv @@ -1,21 +1,11 @@ ////////////////////////////////////////////////////////////////////////////////// // Company: MIET // Engineer: Nikita Bulavin -// -// Create Date: -// Design Name: + // Module Name: tb_cybercobra // Project Name: RISCV_practicum // Target Devices: Nexys A7-100T -// Tool Versions: // Description: tb for CYBERcobra 3000 Pro 2.1 -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// ////////////////////////////////////////////////////////////////////////////////// module tb_CYBERcobra(); diff --git a/Labs/05. Main decoder/tb_decoder_riscv.sv b/Labs/05. Main decoder/tb_decoder_riscv.sv index 59c4936..dd7dcd3 100644 --- a/Labs/05. Main decoder/tb_decoder_riscv.sv +++ b/Labs/05. Main decoder/tb_decoder_riscv.sv @@ -1,21 +1,12 @@ ////////////////////////////////////////////////////////////////////////////////// // Company: MIET // Engineer: Nikita Bulavin -// -// Create Date: -// Design Name: + // Module Name: tb_decoder_riscv // Project Name: RISCV_practicum // Target Devices: Nexys A7-100T -// Tool Versions: + // Description: tb for decoder riscv -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// ////////////////////////////////////////////////////////////////////////////////// module tb_decoder_riscv(); diff --git a/Labs/06. Datapath/tb_riscv_unit.sv b/Labs/06. Datapath/tb_riscv_unit.sv index b648a96..d57f9ca 100644 --- a/Labs/06. Datapath/tb_riscv_unit.sv +++ b/Labs/06. Datapath/tb_riscv_unit.sv @@ -1,21 +1,11 @@ ////////////////////////////////////////////////////////////////////////////////// // Company: MIET // Engineer: Nikita Bulavin -// -// Create Date: -// Design Name: + // Module Name: tb_riscv_unit // Project Name: RISCV_practicum // Target Devices: Nexys A7-100T -// Tool Versions: // Description: tb for datapath -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// ////////////////////////////////////////////////////////////////////////////////// module tb_riscv_unit(); diff --git a/Labs/11. Interrupt integration/tb_irq_unit.sv b/Labs/11. Interrupt integration/tb_irq_unit.sv index 40dc182..9a33e01 100644 --- a/Labs/11. Interrupt integration/tb_irq_unit.sv +++ b/Labs/11. Interrupt integration/tb_irq_unit.sv @@ -1,21 +1,12 @@ ////////////////////////////////////////////////////////////////////////////////// // Company: MIET // Engineer: Andrei Solodovnikov -// -// Create Date: -// Design Name: + // Module Name: tb_riscv_unit // Project Name: RISCV_practicum // Target Devices: Nexys A7-100T -// Tool Versions: // Description: tb for riscv unit with irq support -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// + ////////////////////////////////////////////////////////////////////////////////// module tb_irq_unit(); diff --git a/Labs/12. Peripheral units/testbench.sv b/Labs/12. Peripheral units/testbench.sv index 44bf88b..3342cd0 100644 --- a/Labs/12. Peripheral units/testbench.sv +++ b/Labs/12. Peripheral units/testbench.sv @@ -1,21 +1,12 @@ ////////////////////////////////////////////////////////////////////////////////// // Company: MIET // Engineer: Nikita Bulavin -// -// Create Date: -// Design Name: + // Module Name: tb_riscv_unit // Project Name: RISCV_practicum // Target Devices: Nexys A7-100T -// Tool Versions: + // Description: tb for peripheral units -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// ////////////////////////////////////////////////////////////////////////////////// module tb_riscv_unit(); diff --git a/Labs/Made-up modules/lab_05.decoder.sv b/Labs/Made-up modules/lab_05.decoder.sv index d69d26e..de2b932 100644 --- a/Labs/Made-up modules/lab_05.decoder.sv +++ b/Labs/Made-up modules/lab_05.decoder.sv @@ -1,21 +1,11 @@ ////////////////////////////////////////////////////////////////////////////////// // Company: MIET // Engineer: Alexey Kozin -// -// Create Date: 10/08/2023 07:39:15 AM -// Design Name: + // Module Name: decoder_riscv // Project Name: RISCV_practicum // Target Devices: Nexys A7-100T -// Tool Versions: // Description: main decoder for risc-v processor -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// ////////////////////////////////////////////////////////////////////////////////// module gpr_we_table (gis_ew_rpg, edocpo_6, edocpo_5, edocpo_4, edocpo_3, edocpo_2);