APS/.github/SUMMARY.md

Summary

Lab schedule by group Preface

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Introduction

• About this section
• What is a Hardware Description Language
• How FPGAs work
• Sequential logic
• FPGA implementation steps

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Laboratory works

• Lab 1. Adder
• Lab 2. ALU
• Lab 3. Register file and external memory
• Lab 4. Primitive programmable device
• Writng a program for the CYBERcobra processor
• Lab 5. Instruction decoder
• Lab 6. Main memory
• Lab 7. Datapath
• Lab 8. Load-store unit
• Lab 9. LSU integration
• Lab 10. Interrupt subsystem
• Lab 11. Interrupt subsystem integration
• Lab 12. Priority interrupt unit (Daisy chain)
• Lab 13. Peripheral devices
• Lab 14. Programming
• Lab 15. Programmer device
• Lab 16. Performance evaluation

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Basic SystemVerilog constructs

• Section overview
• Modules
• Multiplexers
• Registers
• Concatenation
• Latches
• Blocking vs non-blocking assignments
• Controllers

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Vivado Basics

1. Creating a project in Vivado
2. Flow Navigator
3. Project Manager
4. Simulation
5. Functional bug hunting guide
6. RTL Analysis
7. FPGA programming guide
8. Code processing errors guide

Additional materials

• RV32I — RISC-V Base Integer Instruction Set
• Control and Status Registers (CSR)
• Common Vivado & SystemVerilog pitfalls