# Summary

[Lab schedule by group](index.md)
[Preface](Intro.md)

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# Introduction

- [About this section](Introduction/README.md)
- [What is a Hardware Description Language](Introduction/What%20is%20HDL.md)
- [How FPGAs work](Introduction/How%20FPGA%20works.md)
- [Sequential logic](Introduction/Sequential%20logic.md)
- [FPGA implementation steps](Introduction/Implementation%20steps.md)

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# Laboratory works

- [Lab 1. Adder](Labs/01.%20Adder/README.md)
- [Lab 2. ALU](Labs/02.%20Arithmetic-logic%20unit/README.md)
- [Lab 3. Register file and external memory](Labs/03.%20Regiter%20file%20and%20memory/README.md)
- [Lab 4. Primitive programmable device](Labs/04.%20Primtive%20programmable%20device/README.md)
- [Writng a program for the CYBERcobra processor](Labs/04.%20Primtive%20programmable%20device/Индивидуальное%20задание/README.md)
- [Lab 5. Instruction decoder](Labs/05.%20Main%20decoder/README.md)
- [Lab 6. Main memory](Labs/06.%20Main%20memory/README.md)
- [Lab 7. Datapath](Labs/07.%20Datapath/README.md)
- [Lab 8. Load-store unit](Labs/08.%20Load-store%20unit/README.md)
- [Lab 9. LSU integration](Labs/09.%20LSU%20Integration/README.md)
- [Lab 10. Interrupt subsystem](Labs/10.%20Interrupt%20subsystem/README.md)
- [Lab 11. Interrupt subsystem integration](Labs/11.%20Interrupt%20integration/README.md)
- [Lab 12. Priority interrupt unit (Daisy chain)](Labs/12.%20Daisy%20chain/README.md)
- [Lab 13. Peripheral devices](Labs/13.%20Peripheral%20units/README.md)
- [Lab 14. Programming](Labs/14.%20Programming/README.md)
- [Lab 15. Programmer device](Labs/15.%20Programming%20device/README.md)
- [Lab 16. Performance evaluation](Labs/16.%20Coremark/README.md)

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# Basic SystemVerilog constructs

- [Section overview](Basic%20Verilog%20structures/README.md)
- [Modules](Basic%20Verilog%20structures/Modules.md)
- [Multiplexers](Basic%20Verilog%20structures/Multiplexors.md)
- [Registers](Basic%20Verilog%20structures/Registers.md)
- [Concatenation](Basic%20Verilog%20structures/Concatenation.md)
- [Latches](Basic%20Verilog%20structures/Latches.md)
- [Blocking vs non-blocking assignments](Basic%20Verilog%20structures/Assignments.md)
- [Controllers](Basic%20Verilog%20structures/Controllers.md)

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# Vivado Basics

1. [Creating a project in Vivado](Vivado%20Basics/01.%20New%20project.md)
2. [Flow Navigator](Vivado%20Basics/02.%20Flow%20Navigator.md)
3. [Project Manager](Vivado%20Basics/03.%20Project%20manager.md)
4. [Simulation](Vivado%20Basics/04.%20Simulation.md)
5. [Functional bug hunting guide](Vivado%20Basics/05.%20Bug%20hunting.md)
6. [RTL Analysis](Vivado%20Basics/06.%20RTL%20Analysis.md)
7. [FPGA programming guide](Vivado%20Basics/07.%20Program%20and%20debug.md)
8. [Code processing errors guide](Vivado%20Basics/08.%20Code%20processing%20errors.md)

# Additional materials

- [RV32I — RISC-V Base Integer Instruction Set](Other/rv32i.md)
- [Control and Status Registers (CSR)](Other/CSR.md)
- [Common Vivado & SystemVerilog pitfalls](Other/FAQ.md)