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Добавление кредитов в исходники

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This commit is contained in:
Andrei Solodovnikov
2024-02-21 11:48:18 +03:00
parent a01446eb43
commit 3dcb0b76f9
67 changed files with 686 additions and 251 deletions
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10
Labs/16. Coremark/Makefile
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@@ -1,3 +1,13 @@
# -----------------------------------------------------------------------------
# Project Name : Architectures of Processor Systems (APS) lab work
# Organization : National Research University of Electronic Technology (MIET)
# Department : Institute of Microdevices and Control Systems
# Author(s) : Andrei Solodovnikov
# Email(s) : hepoh@org.miet.ru
#
# See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
# ------------------------------------------------------------------------------
#
CC_PATH = /c/riscv_cc/bin
CC_PREFIX = riscv-none-elf

10
Labs/16. Coremark/linker_script.ld
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@@ -1,3 +1,13 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
OUTPUT_FORMAT("elf32-littleriscv") /* Указываем порядок следования байт */
ENTRY(_start) /* мы сообщаем компоновщику, что первая

10
Labs/16. Coremark/startup.S
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@@ -1,3 +1,13 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
.section .boot
.global _start

19
Labs/16. Coremark/tb_coremark.sv
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@@ -1,14 +1,13 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Solodovnikov Andrei
// Module Name: tb_coremark
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Description: tb for running Coremark
//
//////////////////////////////////////////////////////////////////////////////////
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module tb_coremark();
logic clk10mhz_i;

19
Labs/16. Coremark/tb_timer.sv
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@@ -1,14 +1,13 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Solodovnikov Andrei
// Module Name: tb_timer
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Description: tb for timer
//
//////////////////////////////////////////////////////////////////////////////////
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module tb_timer();
logic clk_i;