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Добавление кредитов в исходники

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This commit is contained in:
Andrei Solodovnikov
2024-02-21 11:48:18 +03:00
parent a01446eb43
commit 3dcb0b76f9
67 changed files with 686 additions and 251 deletions
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14
Labs/04. Primitive programmable device/board files/nexys_cybercobra.sv
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@@ -1,12 +1,22 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Nikita Bulavin
* Email(s) : nekkit6@edu.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module nexys_CYBERcobra_dz(
input CLK100,
input resetn,
input BTND,
input [15:0] SW,
output CA, CB, CC, CD, CE, CF, CG,
output CA, CB, CC, CD, CE, CF, CG,
output [7:0] AN
);
CYBERcobra dut(
.clk_i(btn),
.rst_i(!resetn),

14
Labs/04. Primitive programmable device/board files/nexys_cybercobra_demo.sv
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@@ -1,12 +1,22 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Nikita Bulavin
* Email(s) : nekkit6@edu.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module nexys_CYBERcobra(
input CLK100,
input resetn,
input BTND,
input [15:0] SW,
output CA, CB, CC, CD, CE, CF, CG,
output CA, CB, CC, CD, CE, CF, CG,
output [7:0] AN
);
CYBERcobra dut(
.clk_i(CLK100),
.rst_i(!resetn),

28
Labs/04. Primitive programmable device/tb_cybercobra.sv
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@@ -1,22 +1,22 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Nikita Bulavin
// Module Name: tb_cybercobra
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Description: tb for CYBERcobra 3000 Pro 2.1
//////////////////////////////////////////////////////////////////////////////////
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Nikita Bulavin
* Email(s) : nekkit6@edu.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module tb_CYBERcobra();
CYBERcobra dut(
.clk_i(clk),
.rst_i(rstn),
.sw_i (sw_i ),
.out_o(OUT)
);
wire [31:0] OUT;
reg clk;
reg rstn;
@@ -24,8 +24,8 @@ module tb_CYBERcobra();
initial clk <= 0;
always #5 clk = ~clk;
initial begin
initial begin
$display( "\nStart test: \n\n===============================================\nAdd CYBERcobra signals to the waveform and then\nCLICK THE BUTTON 'Run All'\n===============================================\n"); $stop();
rstn = 1'b1;
#10;
@@ -37,5 +37,5 @@ module tb_CYBERcobra();
$display("\n The test is over \n See the internal signals of the CYBERcobra on the waveform \n");
$finish;
end
endmodule