Добавление кредитов в исходники

Labs/03. Register file and memory/tb_data_mem.sv

@@ -1,13 +1,13 @@
-//////////////////////////////////////////////////////////////////////////////////
-// Company: MIET
-// Engineer: Nikita Bulavin
-
-// Module Name:    tb_data_mem
-// Project Name:   RISCV_practicum
-// Target Devices: Nexys A7-100T
-// Description: tb for data memory
-//////////////////////////////////////////////////////////////////////////////////
+/* -----------------------------------------------------------------------------
+* Project Name   : Architectures of Processor Systems (APS) lab work
+* Organization   : National Research University of Electronic Technology (MIET)
+* Department     : Institute of Microdevices and Control Systems
+* Author(s)      : Nikita Bulavin
+* Email(s)       : nekkit6@edu.miet.ru
 
+See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
+* ------------------------------------------------------------------------------
+*/
 module tb_data_mem();
 
 parameter ADDR_SIZE = 16384;