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13 lines
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13 lines
1.1 KiB
Markdown
# Basic Verilog Language Constructs
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These files contain information that, once mastered, will allow you to complete the first lab assignments without difficulty.
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The recommended reading order is as follows:
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1. For the first lab assignment, you need to understand how a basic module is described and how [combinational logic](https://en.wikipedia.org/wiki/Combinational_logic) is built using continuous assignments. This is covered in the document [Modules.md](Modules.md).
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2. For the second lab assignment, you need to be able to write a basic module (see item 1) and describe a combinational block such as a [multiplexer](https://en.wikipedia.org/wiki/Multiplexer). This is covered in the document [Multiplexors.md](./Multiplexors.md).
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3. For the third lab assignment, in addition to the above, you need to know how to describe the basic memory element — a register — and how to group signals (concatenation). These topics are covered in [Registers.md](./Registers.md) and [Concatenation.md](./Concatenation.md) respectively.
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Knowledge from all of these documents is required for all subsequent lab assignments.
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Good luck with your preparation!
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