# Basic Verilog Language Constructs

These files contain information that, once mastered, will allow you to complete the first lab assignments without difficulty.
The recommended reading order is as follows:

1. For the first lab assignment, you need to understand how a basic module is described and how [combinational logic](https://en.wikipedia.org/wiki/Combinational_logic) is built using continuous assignments. This is covered in the document [Modules.md](Modules.md).
2. For the second lab assignment, you need to be able to write a basic module (see item 1) and describe a combinational block such as a [multiplexer](https://en.wikipedia.org/wiki/Multiplexer). This is covered in the document [Multiplexors.md](./Multiplexors.md).
3. For the third lab assignment, in addition to the above, you need to know how to describe the basic memory element — a register — and how to group signals (concatenation). These topics are covered in [Registers.md](./Registers.md) and [Concatenation.md](./Concatenation.md) respectively.

Knowledge from all of these documents is required for all subsequent lab assignments.

Good luck with your preparation!