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ЛР6. Исправление прототипа riscv_unit

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Andrei Solodovnikov
2023-10-15 10:51:51 +03:00
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parent a923ff2ea8
commit f9507694b9
1 changed files with 1 additions and 1 deletions
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Labs/06. Datapath/README.md
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@@ -61,7 +61,7 @@ endmodule
```SystemVerilog ```SystemVerilog
module riscv_unit( module riscv_unit(
input logic clk_i, input logic clk_i,
input logic resetn_i input logic rst_i
); );
endmodule endmodule