diff --git a/Labs/06. Datapath/README.md b/Labs/06. Datapath/README.md
index 066db62..b7fd706 100644
--- a/Labs/06. Datapath/README.md	
+++ b/Labs/06. Datapath/README.md	
@@ -61,7 +61,7 @@ endmodule
 ```SystemVerilog
 module riscv_unit(
   input  logic        clk_i,
-  input  logic        resetn_i
+  input  logic        rst_i
 );
 
 endmodule