From f9507694b9db08645a9efb8cd177c48aa5e2461d Mon Sep 17 00:00:00 2001
From: Andrei Solodovnikov <VoultBoy@yandex.ru>
Date: Sun, 15 Oct 2023 10:51:51 +0300
Subject: [PATCH] =?UTF-8?q?=D0=9B=D0=A06.=20=D0=98=D1=81=D0=BF=D1=80=D0=B0?=
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 =?UTF-8?q?=D0=BE=D1=82=D0=B8=D0=BF=D0=B0=20riscv=5Funit?=
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---
 Labs/06. Datapath/README.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Labs/06. Datapath/README.md b/Labs/06. Datapath/README.md
index 066db62..b7fd706 100644
--- a/Labs/06. Datapath/README.md	
+++ b/Labs/06. Datapath/README.md	
@@ -61,7 +61,7 @@ endmodule
 ```SystemVerilog
 module riscv_unit(
   input  logic        clk_i,
-  input  logic        resetn_i
+  input  logic        rst_i
 );
 
 endmodule