Initial commit

Labs/07. Load-store unit/README.md

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+# Лабораторная работа 5 "Блок загрузки и сохранения"
+
+## Цель
+
+--
+
+## Ход работы
+
+--
+
+## Теория
+
+==
+
+## Практика
+
+--
+
+## Задание
+
+--
+
+### Порядок выполнения задания
+
+--

Labs/07. Load-store unit/miriscv_ram.sv

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+module miriscv_ram
+#(
+  parameter RAM_SIZE      = 256, // bytes
+  parameter RAM_INIT_FILE = ""
+)
+(
+  // clock, reset
+  input clk_i,
+  input rst_n_i,
+
+  // instruction memory interface
+  output logic  [31:0]  instr_rdata_o,
+  input         [31:0]  instr_addr_i,
+
+  // data memory interface
+  output logic  [31:0]  data_rdata_o,
+  input                 data_req_i,
+  input                 data_we_i,
+  input         [3:0]   data_be_i,
+  input         [31:0]  data_addr_i,
+  input         [31:0]  data_wdata_i
+);
+
+  reg [31:0]    mem [0:RAM_SIZE/4-1];
+  reg [31:0]    data_int;
+
+  //Init RAM
+  integer ram_index;
+
+  initial begin
+    if(RAM_INIT_FILE != "")
+      $readmemh(RAM_INIT_FILE, mem);
+    else
+      for (ram_index = 0; ram_index < RAM_SIZE/4-1; ram_index = ram_index + 1)
+        mem[ram_index] = {32{1'b0}};
+  end
+
+
+  //Instruction port
+  assign instr_rdata_o = mem[(instr_addr_i % RAM_SIZE) / 4];
+
+  always@(posedge clk_i) begin
+    if(!rst_n_i) begin
+      data_rdata_o  <= 32'b0;
+    end
+    else if(data_req_i) begin
+      data_rdata_o <= mem[(data_addr_i  % RAM_SIZE) / 4];
+
+      if(data_we_i && data_be_i[0])
+        mem [data_addr_i[31:2]] [7:0]  <= data_wdata_i[7:0];
+
+      if(data_we_i && data_be_i[1])
+        mem [data_addr_i[31:2]] [15:8] <= data_wdata_i[15:8];
+
+      if(data_we_i && data_be_i[2])
+        mem [data_addr_i[31:2]] [23:16] <= data_wdata_i[23:16];
+
+      if(data_we_i && data_be_i[3])
+        mem [data_addr_i[31:2]] [31:24] <= data_wdata_i[31:24];
+
+    end
+  end
+
+
+endmodule

Labs/07. Load-store unit/miriscv_top.sv

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+module miriscv_top
+#(
+  parameter RAM_SIZE      = 256, // bytes
+  parameter RAM_INIT_FILE = ""
+)
+(
+  // clock, reset
+  input clk_i,
+  input rst_n_i
+);
+
+  logic  [31:0]  instr_rdata_core;
+  logic  [31:0]  instr_addr_core;
+
+  logic  [31:0]  data_rdata_core;
+  logic          data_req_core;
+  logic          data_we_core;
+  logic  [3:0]   data_be_core;
+  logic  [31:0]  data_addr_core;
+  logic  [31:0]  data_wdata_core;
+
+  logic  [31:0]  data_rdata_ram;
+  logic          data_req_ram;
+  logic          data_we_ram;
+  logic  [3:0]   data_be_ram;
+  logic  [31:0]  data_addr_ram;
+  logic  [31:0]  data_wdata_ram;
+
+  logic  data_mem_valid;
+  assign data_mem_valid = (data_addr_core >= RAM_SIZE) ?  1'b0 : 1'b1;
+
+  assign data_rdata_core  = (data_mem_valid) ? data_rdata_ram : 1'b0;
+  assign data_req_ram     = (data_mem_valid) ? data_req_core : 1'b0;
+  assign data_we_ram      =  data_we_core;
+  assign data_be_ram      =  data_be_core;
+  assign data_addr_ram    =  data_addr_core;
+  assign data_wdata_ram   =  data_wdata_core;
+
+  miriscv_core core (
+    .clk_i   ( clk_i   ),
+    .arstn_i ( rst_n_i ),
+
+    .instr_rdata_i ( instr_rdata_core ),
+    .instr_addr_o  ( instr_addr_core  ),
+
+    .data_rdata_i  ( data_rdata_core  ),
+    .data_req_o    ( data_req_core    ),
+    .data_we_o     ( data_we_core     ),
+    .data_be_o     ( data_be_core     ),
+    .data_addr_o   ( data_addr_core   ),
+    .data_wdata_o  ( data_wdata_core  )
+  );
+
+  miriscv_ram
+  #(
+    .RAM_SIZE      (RAM_SIZE),
+    .RAM_INIT_FILE (RAM_INIT_FILE)
+  ) ram (
+    .clk_i   ( clk_i   ),
+    .rst_n_i ( rst_n_i ),
+
+    .instr_rdata_o ( instr_rdata_core ),
+    .instr_addr_i  ( instr_addr_core  ),
+
+    .data_rdata_o  ( data_rdata_ram  ),
+    .data_req_i    ( data_req_ram    ),
+    .data_we_i     ( data_we_ram     ),
+    .data_be_i     ( data_be_ram     ),
+    .data_addr_i   ( data_addr_ram   ),
+    .data_wdata_i  ( data_wdata_ram  )
+  );
+
+
+endmodule

Labs/07. Load-store unit/tb_miriscv_top.v

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+`timescale 1ns / 1ps
+
+module tb_miriscv_top();
+
+  parameter     HF_CYCLE = 2.5;       // 200 MHz clock
+  parameter     RST_WAIT = 10;         // 10 ns reset
+  parameter     RAM_SIZE = 512;       // in 32-bit words
+
+  // clock, reset
+  reg clk;
+  reg rst_n;
+
+  miriscv_top #(
+    .RAM_SIZE       ( RAM_SIZE           ),
+    .RAM_INIT_FILE  ( "program_sort.dat" )
+  ) dut (
+    .clk_i    ( clk   ),
+    .rst_n_i  ( rst_n )
+  );
+
+  initial begin
+    clk   = 1'b0;
+    rst_n = 1'b0;
+    #RST_WAIT;
+    rst_n = 1'b1;
+  end
+
+  always begin
+    #HF_CYCLE;
+    clk = ~clk;
+  end
+
+endmodule