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34 lines
582 B
Verilog
34 lines
582 B
Verilog
`timescale 1ns / 1ps
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module tb_miriscv_top();
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parameter HF_CYCLE = 2.5; // 200 MHz clock
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parameter RST_WAIT = 10; // 10 ns reset
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parameter RAM_SIZE = 512; // in 32-bit words
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// clock, reset
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reg clk;
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reg rst_n;
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miriscv_top #(
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.RAM_SIZE ( RAM_SIZE ),
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.RAM_INIT_FILE ( "program_sort.dat" )
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) dut (
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.clk_i ( clk ),
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.rst_n_i ( rst_n )
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);
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initial begin
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clk = 1'b0;
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rst_n = 1'b0;
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#RST_WAIT;
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rst_n = 1'b1;
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end
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always begin
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#HF_CYCLE;
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clk = ~clk;
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end
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endmodule
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