Translate Basic Verilog structures pictures to english

Browse Source

...

This commit is contained in:

footbooller

2026-06-24 01:05:44 +03:00

committed by GitHub

parent f3fcd27387

commit a5397a4495

4 changed files with 8 additions and 465 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download Patch File Download Diff File Expand all files Collapse all files

308

.pic/Basic Verilog structures/assignments/fig_03.drawio.svg

File diff suppressed because one or more lines are too long

Side by Side Swipe Overlay Before Width:  |  Height:  |  Size: 24 KiB After Width:  |  Height:  |  Size: 29 KiB

165

.pic/Basic Verilog structures/assignments/fig_14.drawio.svg

File diff suppressed because one or more lines are too long

Side by Side Swipe Overlay Before Width:  |  Height:  |  Size: 85 KiB After Width:  |  Height:  |  Size: 142 KiB

BIN

.pic/Basic Verilog structures/testbench/tb_1.png

Binary file not shown.

Side by Side Swipe Overlay Before Width:  |  Height:  |  Size: 64 KiB After Width:  |  Height:  |  Size: 42 KiB

BIN

.pic/Basic Verilog structures/verilog syntax/file_structure.png

Binary file not shown.

Side by Side Swipe Overlay Before Width:  |  Height:  |  Size: 66 KiB After Width:  |  Height:  |  Size: 93 KiB