diff --git a/.pic/Basic Verilog structures/assignments/fig_03.drawio.svg b/.pic/Basic Verilog structures/assignments/fig_03.drawio.svg index 4871d7b..2ca9de6 100644 --- a/.pic/Basic Verilog structures/assignments/fig_03.drawio.svg +++ b/.pic/Basic Verilog structures/assignments/fig_03.drawio.svg @@ -1,304 +1,4 @@ - - - - - - - -
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- - module - - - blocking_assignment - - - ( - -
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- - - - output - - - - - logic - - - c, d - -
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- - ); - -
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- - // блокирующее присваивание -
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- - always_ff - - - @(posedge clk) begin - -
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- - - - b = a; - -
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- - c = b; - - - // обновленное значение b - -
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- - d = c; - - - // обновленное значение с - -
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- - end - -
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- - - module blocking_assignment(... - - - - - - - -
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- - ); - -
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- - // неблокирующее присваивание -
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- - always_ff - - - @(posedge clk) begin - -
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- - - - b <= a; - -
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- - c <= b; - - - // старое значение b - -
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- - d <= c; - - - // старое значение c - -
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- - end - -
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- - - module nonblocking_assignment(... - - - - - - - - - - - - - - - - - - - - - - - - - Text is not SVG - cannot display - - - - \ No newline at end of file + + + +
module blocking_assignment(
  input  logic a, b
  output logic c, d
);

// blocking assignment
always_ff @(posedge clk) begin
  b = a;

  c = b;  // updated value of b

  d = c;  // updated value of с
end

endmodule
module blocking_assignment(...
module nonblocking_assignment(
  input  logic a, b
  output logic c, d
);

// non-blocking assignment
always_ff @(posedge clk) begin
  b <= a;

  c <= b;  // old value of b

  d <= c;  // old value of c
end

endmodule
module nonblocking_assignment(...Text is not SVG - cannot display \ No newline at end of file diff --git a/.pic/Basic Verilog structures/assignments/fig_14.drawio.svg b/.pic/Basic Verilog structures/assignments/fig_14.drawio.svg index 76320dc..6674ef3 100644 --- a/.pic/Basic Verilog structures/assignments/fig_14.drawio.svg +++ b/.pic/Basic Verilog structures/assignments/fig_14.drawio.svg @@ -1,161 +1,4 @@ - - - - - - - -
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- - always_comb begin - -
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- - temp - - <= a | b; -
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- - d - - <= c & temp; -
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- - end - -
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- - - Второй проход блока always - - - - - - - - - - Text is not SVG - cannot display - - - - \ No newline at end of file + + + +
logic [31:0] a,b,c;
always_comb begin
  temp <= a | b;
  d    <= c & temp;
end
logic [31:0] a,b,c;...
5ns
5ns
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5ns
first pass of the always block
first pass of the...
second pass of the always block
second pass of the...Text is not SVG - cannot display \ No newline at end of file diff --git a/.pic/Basic Verilog structures/testbench/tb_1.png b/.pic/Basic Verilog structures/testbench/tb_1.png index eeba199..6f225f7 100644 Binary files a/.pic/Basic Verilog structures/testbench/tb_1.png and b/.pic/Basic Verilog structures/testbench/tb_1.png differ diff --git a/.pic/Basic Verilog structures/verilog syntax/file_structure.png b/.pic/Basic Verilog structures/verilog syntax/file_structure.png index aa9dc62..7ad7f81 100644 Binary files a/.pic/Basic Verilog structures/verilog syntax/file_structure.png and b/.pic/Basic Verilog structures/verilog syntax/file_structure.png differ