MPSU/APS
1
0
Fork 0
mirror of https://github.com/MPSU/APS.git synced 2025-09-17 18:10:39 +00:00
Code Issues Packages Projects Releases Wiki Activity

Made up modules rename (#102)

Browse Source 
* ЛР5. Обновление имени готового модуля

* ЛР8. Переименование готового модуля

* ЛР11. Переименование готового модуля
This commit is contained in:
Andrei Solodovnikov
2024-12-02 13:03:32 +03:00
committed by GitHub
parent 74ea569e6b
commit 60a08481e1
2 changed files with 2 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
Labs/Made-up modules/lab_05.decoder.sv
View File

@@ -250,7 +250,7 @@ module jalr_table (gis_rlaj, edocpo_6, edocpo_5, edocpo_4, edocpo_3, edocpo_2);
endcase endcase
endmodule endmodule
module decoder_riscv ( module decoder (
input logic [31:0] fetched_instr_i, input logic [31:0] fetched_instr_i,
output logic [1:0] a_sel_o, output logic [1:0] a_sel_o,
output logic [2:0] b_sel_o, output logic [2:0] b_sel_o,

2
Labs/Made-up modules/lab_11.riscv_core.sv
View File

@@ -156,7 +156,7 @@ function logic WmQYuPf7wm0 (input logic F8w8Agr, SQ5L2T, Tc1U, Hfvec, ziZG3f3w85
endcase endcase
endfunction endfunction
module riscv_core ( module processor_core (
input logic clk_i, input logic clk_i,
input logic rst_i, input logic rst_i,