From 60a08481e1828d69d69f59747daeafb01bed9fb2 Mon Sep 17 00:00:00 2001 From: Andrei Solodovnikov Date: Mon, 2 Dec 2024 13:03:32 +0300 Subject: [PATCH] Made up modules rename (#102) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * ЛР5. Обновление имени готового модуля * ЛР8. Переименование готового модуля * ЛР11. Переименование готового модуля --- Labs/Made-up modules/lab_05.decoder.sv | 2 +- Labs/Made-up modules/lab_11.riscv_core.sv | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Labs/Made-up modules/lab_05.decoder.sv b/Labs/Made-up modules/lab_05.decoder.sv index c7176aa..a718975 100644 --- a/Labs/Made-up modules/lab_05.decoder.sv +++ b/Labs/Made-up modules/lab_05.decoder.sv @@ -250,7 +250,7 @@ module jalr_table (gis_rlaj, edocpo_6, edocpo_5, edocpo_4, edocpo_3, edocpo_2); endcase endmodule -module decoder_riscv ( +module decoder ( input logic [31:0] fetched_instr_i, output logic [1:0] a_sel_o, output logic [2:0] b_sel_o, diff --git a/Labs/Made-up modules/lab_11.riscv_core.sv b/Labs/Made-up modules/lab_11.riscv_core.sv index d077079..650a404 100644 --- a/Labs/Made-up modules/lab_11.riscv_core.sv +++ b/Labs/Made-up modules/lab_11.riscv_core.sv @@ -156,7 +156,7 @@ function logic WmQYuPf7wm0 (input logic F8w8Agr, SQ5L2T, Tc1U, Hfvec, ziZG3f3w85 endcase endfunction -module riscv_core ( +module processor_core ( input logic clk_i, input logic rst_i,