diff --git a/Labs/Made-up modules/lab_05.decoder.sv b/Labs/Made-up modules/lab_05.decoder.sv
index c7176aa..a718975 100644
--- a/Labs/Made-up modules/lab_05.decoder.sv	
+++ b/Labs/Made-up modules/lab_05.decoder.sv	
@@ -250,7 +250,7 @@ module jalr_table (gis_rlaj, edocpo_6, edocpo_5, edocpo_4, edocpo_3, edocpo_2);
     endcase
 endmodule
 
-module decoder_riscv (
+module decoder (
     input  logic [31:0] fetched_instr_i,
     output logic [1:0]  a_sel_o,
     output logic [2:0]  b_sel_o,
diff --git a/Labs/Made-up modules/lab_11.riscv_core.sv b/Labs/Made-up modules/lab_11.riscv_core.sv
index d077079..650a404 100644
--- a/Labs/Made-up modules/lab_11.riscv_core.sv	
+++ b/Labs/Made-up modules/lab_11.riscv_core.sv	
@@ -156,7 +156,7 @@ function logic WmQYuPf7wm0 (input logic F8w8Agr, SQ5L2T, Tc1U, Hfvec, ziZG3f3w85
     endcase
 endfunction
 
-module riscv_core (
+module processor_core (
   input  logic        clk_i,
   input  logic        rst_i,