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ЛР13. Обновление vga (#92)
* Fix(vga):Испр-ие чтения из char_tiff * Ref(vgachargen):Испр-ие коммента к clk100m_i * ЛР13. Добавление примечания насчет синхронного чтения в vga_sb_ctrl --------- Co-authored-by: Andrei Solodovnikov <VoultBoy@yandex.ru>
This commit is contained in:
BROsandr
GitHub
@@ -744,8 +744,7 @@ module vgachargen (
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* firmware/mem_files/lab_13_ps2_vga_instr.mem — этим файлом необходимо проинициализировать память инструкций
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* firmware/mem_files/lab_13_ps2ascii_data.mem — этим файлом необходимо проинициализировать память данных
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* firmware/mem_files/lab_13_vga_ch_map.mem
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* firmware/mem_files/lab_13_vga_ch_t_ro.mem
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* firmware/mem_files/lab_13_vga_ch_t_rw.mem
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* firmware/mem_files/lab_13_vga_ch_t.mem
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* firmware/mem_files/lab_13_vga_col_map.mem
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Вам необходимо добавить в проект все эти файлы.
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@@ -802,9 +801,12 @@ module vga_sb_ctrl (
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Оба эти сигнала мультиплексируются / демультиплексируются с помощью одного и того же управляющего сигнала: `addr_i[13:12]` в соответствии с диапазонами адресов (рис. 4):
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* `addr_i[13:12] == 2'b00` — сигнал `write_enable_i` поступает на вход `char_map_we_i`, выход `char_map_rdata_o` записывается в выходной регистр `read_data_o`;
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* `addr_i[13:12] == 2'b01` — сигнал `write_enable_i` поступает на вход `col_map_we_i`, выход `col_map_rdata_o` записывается в выходной регистр `read_data_o`;
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* `addr_i[13:12] == 2'b10` — сигнал `write_enable_i` поступает на вход `char_tiff_we_i`, выход `char_tiff_rdata_o` записывается в выходной регистр `read_data_o`.
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- `addr_i[13:12] == 2'b00` — сигнал `write_enable_i` поступает на вход `char_map_we_i`, выход `char_map_rdata_o` подается на выход `read_data_o`;
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- `addr_i[13:12] == 2'b01` — сигнал `write_enable_i` поступает на вход `col_map_we_i`, выход `col_map_rdata_o` подается на выход `read_data_o`;
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- `addr_i[13:12] == 2'b10` — сигнал `write_enable_i` поступает на вход `char_tiff_we_i`, выход `char_tiff_rdata_o` подается на выход `read_data_o`.
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> [!Important]
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> Обратите внимание на то что, контроллер vga является единственным контроллером, для которого не нужно реализовывать регистр перед выходом read_data_o для реализации синхронного чтения. Данная особенность обусловленна тем, что внутри модуля `vgachargen` уже находится блочная память с синхронным портом на чтение. Добавление еще одного регистра приведет к тому, данные будут "опаздывать" на один такт. Таким образом, данные на выход `read_data_o` необходимо подавать с помощью чисто комбинационной логики.
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## Список использованной литературы
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@@ -597,3 +597,4 @@
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53525150
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57565554
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5b5a5958
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5f5e5d5c
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@@ -1,33 +0,0 @@
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00000000000000000000000000000000000000000000000000000000000000000000000001000010010000100111111001000010001001000010010000011000
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00000000000000000000000000000000000000000000000000000000000000000000000000111110010000100100001000111110000000100000001000111110
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00000000000000000000000000000000000000000000000000000000000000000000000000111110010000100100001000111110001000100010001000011110
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00000000000000000000000000000000000000000000000000000000000000000000000000000010000000100000001000000010000000100000001001111110
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00000000000000000000000000000000000000000000000000000000000000000100000101111111001000010010001000100010001001000010010000111100
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00000000000000000000000000000000000000000000000000000000000000000000000001111110000000100000001000011110000000100000001001111110
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00000000000000000000000000000000000000000000000000000000000000000000000001111110000000100000001000011110000000100111111000100100
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00000000000000000000000000000000000000000000000000000000000000000000000001001001010010010010101000011100001010100100100101001001
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00000000000000000000000000000000000000000000000000000000000000000000000000111100010000100100000000111000010000000100010000111000
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00000000000000000000000000000000000000000000000000000000000000000000000001000110010010100100101001010010010100100110001001100010
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00000000000000000000000000000000000000000000000000000000000000000000000001000110010010100101001001100010010000100001100000100100
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00000000000000000000000000000000000000000000000000000000000000000000000001000010001000100010001000011110000010100001001000100010
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00000000000000000000000000000000000000000000000000000000000000000000000001000010010000100100010001000100010010000100100001111000
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00000000000000000000000000000000000000000000000000000000000000000000000001001001010010010101010101010101011000110110001101000001
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00000000000000000000000000000000000000000000000000000000000000000000000001000010010000100100001001111110010000100100001001000010
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00000000000000000000000000000000000000000000000000000000000000000000000000011100001000100100001001000010010000100100010000111000
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00000000000000000000000000000000000000000000000000000000000000000000000001000010010000100100001001000010010000100100001001111110
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00000000000000000000000000000000000000000000000000000000000000000000000000000010000000100001111000100010010000100100001000111110
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00000000000000000000000000000000000000000000000000000000000000000000000000111000010001000000001000000010000000100100010000111000
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00000000000000000000000000000000000000000000000000000000000000000000000000001000000010000000100000001000000010000000100001111111
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00000000000000000000000000000000000000000000000000000000000000000000000000000010000001000000100000011000001001000100001001000010
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00000000000000000000000000000000000000000000000000000000000000000000000000001000001111100100100101001001010010010011111000001000
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00000000000000000000000000000000000000000000000000000000000000000000000001000010010000100010010000011000001001000100001001000010
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00000000000000000000000000000000000000000000000000000000000000000100000001111110001000100010001000100010001000100010001000100010
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00000000000000000000000000000000000000000000000000000000000000000000000001000000010000000101110001100010010000100100001001000010
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00000000000000000000000000000000000000000000000000000000000000000000000001111111010010010100100101001001010010010100100101001001
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00000000000000000000000000000000000000000000000000000000000000000100000001111111010010010100100101001001010010010100100101001001
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00000000000000000000000000000000000000000000000000000000000000000000000000111100010001000100010001000100001111000000010000000111
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00000000000000000000000000000000000000000000000000000000000000000000000001001111010100010101000101010001010011110100000101000001
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00000000000000000000000000000000000000000000000000000000000000000000000000011110001000100010001000100010000111100000001000000010
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00000000000000000000000000000000000000000000000000000000000000000000000000011100001000100100000001111000010000000010001000011100
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00000000000000000000000000000000000000000000000000000000000000000000000000011001001001010100010101000111010001010100100100110001
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00000000000000000000000000000000000000000000000000000000000000000000000001000010010001000111110001000010010000100100010001111000
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@@ -12,14 +12,12 @@ module vgachargen
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import vgachargen_pkg::*;
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#(
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parameter int unsigned CLK_FACTOR_25M = 100 / 25,
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parameter CH_T_RO_INIT_FILE_NAME = "lab_13_vga_ch_t_ro.mem",
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parameter bit CH_T_RO_INIT_FILE_IS_BIN = 1,
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parameter CH_T_RW_INIT_FILE_NAME = "lab_13_vga_ch_t_rw.mem",
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parameter bit CH_T_RW_INIT_FILE_IS_BIN = 1,
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parameter CH_T_INIT_FILE_NAME = "lab_13_vga_ch_t.mem",
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parameter bit CH_T_INIT_FILE_IS_BIN = 1'b1,
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parameter CH_MAP_INIT_FILE_NAME = "lab_13_vga_ch_map.mem",
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parameter bit CH_MAP_INIT_FILE_IS_BIN = 0,
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parameter bit CH_MAP_INIT_FILE_IS_BIN = 1'b0,
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parameter COL_MAP_INIT_FILE_NAME = "lab_13_vga_col_map.mem",
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parameter bit COL_MAP_INIT_FILE_IS_BIN = 0
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parameter bit COL_MAP_INIT_FILE_IS_BIN = 1'b0
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) (
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input logic clk_i, // системный синхроимпульс
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input logic clk100m_i, // клок с частотой 100МГц
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@@ -58,6 +56,10 @@ module vgachargen
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output logic vga_hs_o, // линия горизонтальной синхронизации vga
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output logic vga_vs_o // линия вертикальной синхронизации vga
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);
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logic vga_clk_i;
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assign vga_clk_i = clk100m_i;
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if (CLK_FACTOR_25M == 0 || CLK_FACTOR_25M > 4) error_unsupported_factor error_unsupported_factor ();
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logic [3:0] char_map_be_gated;
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assign char_map_be_gated = char_map_be_i & {4{char_map_we_i}};
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@@ -65,6 +67,9 @@ module vgachargen
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logic [3:0] col_map_be_gated;
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assign col_map_be_gated = col_map_be_i & {4{col_map_we_i}};
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logic [3:0] char_tiff_be_gated;
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assign char_tiff_be_gated = char_tiff_be_i & {4{char_tiff_we_i}};
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logic arstn_i;
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assign arstn_i = ~rst_i;
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@@ -78,7 +83,7 @@ module vgachargen
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.DATA_WIDTH (1),
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.DELAY_BY (2)
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) pixel_enable_delay (
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.clk_i (clk100m_i),
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.clk_i (vga_clk_i),
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.arstn_i (arstn_i),
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.data_i (pixel_enable),
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.data_o (pixel_enable_delayed)
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@@ -91,7 +96,7 @@ module vgachargen
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.DATA_WIDTH (1),
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.DELAY_BY (2)
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) vga_vs_delay (
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.clk_i (clk100m_i),
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.clk_i (vga_clk_i),
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.arstn_i (arstn_i),
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.data_i (vga_vs),
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.data_o (vga_vs_delayed)
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@@ -104,7 +109,7 @@ module vgachargen
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.DATA_WIDTH (1),
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.DELAY_BY (2)
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) vga_hs_delay (
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.clk_i (clk100m_i),
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.clk_i (vga_clk_i),
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.arstn_i (arstn_i),
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.data_i (vga_hs),
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.data_o (vga_hs_delayed)
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@@ -114,7 +119,7 @@ module vgachargen
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vga_block #(
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.CLK_FACTOR_25M (CLK_FACTOR_25M)
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) vga_block (
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.clk_i (clk100m_i),
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.clk_i (vga_clk_i),
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.arstn_i (arstn_i),
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.hcount_o (hcount_pixels),
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.vcount_o (vcount_pixels),
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@@ -132,7 +137,7 @@ module vgachargen
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.DATA_WIDTH (BITMAP_ADDR_WIDTH),
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.DELAY_BY (2)
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) bitmap_delay (
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.clk_i (clk100m_i),
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.clk_i (vga_clk_i),
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.arstn_i (arstn_i),
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.data_i (bitmap_addr),
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.data_o (bitmap_addr_delayed)
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@@ -145,12 +150,25 @@ module vgachargen
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.bitmap_addr_o (bitmap_addr)
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);
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logic [1:0] ch_map_byte_select;
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logic [1:0] ch_map_byte_select_delayed;
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assign ch_map_byte_select = ch_map_addr_internal[1:0];
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logic [CH_T_ADDR_WIDTH:0] ch_t_addr_internal;
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delay #(
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.DATA_WIDTH (2),
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.DELAY_BY (1)
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) ch_map_byte_select_delay (
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.clk_i (vga_clk_i),
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.arstn_i (arstn_i),
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.data_i (ch_map_byte_select),
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.data_o (ch_map_byte_select_delayed)
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);
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logic [CH_T_ADDR_WIDTH-1:0] ch_t_addr_internal;
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logic [3:0][7:0] ch_map_data_word;
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assign ch_t_addr_internal = ch_map_data_word[ch_map_addr_internal[1:0]];
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assign ch_t_addr_internal = ch_map_data_word[ch_map_byte_select_delayed];
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true_dual_port_rw_bram #(
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.INIT_FILE_NAME (CH_MAP_INIT_FILE_NAME),
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@@ -158,7 +176,7 @@ module vgachargen
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.ADDR_WIDTH (10)
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) ch_map (
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.clka_i (clk_i),
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.clkb_i (clk100m_i),
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.clkb_i (vga_clk_i),
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.addra_i (char_map_addr_i),
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.addrb_i (ch_map_addr_internal[$left(ch_map_addr_internal):2]),
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.wea_i (char_map_be_gated),
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@@ -167,62 +185,68 @@ module vgachargen
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.doutb_o (ch_map_data_word)
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);
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logic [CH_T_ADDR_WIDTH-1:0] ch_t_ro_addr_internal;
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assign ch_t_ro_addr_internal = ch_t_addr_internal[CH_T_ADDR_WIDTH-1:0];
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logic [CH_T_DATA_WIDTH-1:0] ch_t_ro_data_internal;
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logic [CH_T_DATA_WIDTH-1:0] ch_t_data_internal;
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single_port_ro_bram #(
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.INIT_FILE_NAME (CH_T_RO_INIT_FILE_NAME),
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.INIT_FILE_IS_BIN (CH_T_RO_INIT_FILE_IS_BIN),
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.DATA_WIDTH (CH_T_DATA_WIDTH),
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.ADDR_WIDTH (CH_T_ADDR_WIDTH)
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) ch_t_ro (
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.clk_i (clk100m_i),
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.addr_i(ch_t_ro_addr_internal),
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.dout_o(ch_t_ro_data_internal)
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);
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logic [CH_T_ADDR_WIDTH-1:0] char_tiff_addr_128bit;
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assign char_tiff_addr_128bit = char_tiff_addr_i[$left(char_tiff_addr_i):2];
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logic [1:0] char_tiff_addr_offset_32bit;
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assign char_tiff_addr_offset_32bit = char_tiff_addr_i[1:0];
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logic [CH_T_ADDR_WIDTH-1:0] ch_t_rw_addr_internal;
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assign ch_t_rw_addr_internal = ch_t_ro_addr_internal;
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logic [CH_T_DATA_WIDTH-1:0] ch_t_rw_data_internal;
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logic [3:0][3:0] char_tiff_wea;
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always_comb begin : bin2onehot
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char_tiff_wea = '0;
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char_tiff_wea[char_tiff_addr_offset_32bit] = char_tiff_be_gated;
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end
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logic [6:0] char_tiff_addr_offset_128bit;
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logic [6:0] char_tiff_addr_offset_128bit_ff;
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assign char_tiff_addr_offset_128bit = {char_tiff_addr_offset_32bit, 5'b00000};
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logic [127:0] char_tiff_wdata_128bit;
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always_comb begin
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char_tiff_wdata_128bit = '0;
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char_tiff_wdata_128bit[char_tiff_addr_offset_128bit+:32] = char_tiff_wdata_i;
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end
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logic [127:0] char_tiff_rdata_128bit;
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assign char_tiff_rdata_o = char_tiff_rdata_128bit[char_tiff_addr_offset_128bit_ff+:32];
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always_ff @(posedge clk_i) begin
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char_tiff_addr_offset_128bit_ff <= char_tiff_addr_offset_128bit;
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end
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true_dual_port_rw_bram #(
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.INIT_FILE_NAME (CH_T_RW_INIT_FILE_NAME),
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.INIT_FILE_IS_BIN (CH_T_RW_INIT_FILE_IS_BIN),
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.NUM_COLS (1),
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.COL_WIDTH (CH_T_DATA_WIDTH),
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.INIT_FILE_NAME (CH_T_INIT_FILE_NAME),
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.INIT_FILE_IS_BIN (CH_T_INIT_FILE_IS_BIN),
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.NUM_COLS (16),
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.COL_WIDTH (8),
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.ADDR_WIDTH (CH_T_ADDR_WIDTH)
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) ch_t_rw (
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) char_tiff (
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.clka_i (clk_i),
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.clkb_i (clk100m_i),
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// .addra_i (ch_t_rw_addr_i),
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.addra_i (),
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.addrb_i (ch_t_rw_addr_internal),
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// .wea_i (ch_t_rw_wen_i),
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.wea_i (),
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// .dina_i (ch_t_rw_data_i),
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.dina_i (),
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// .douta_o (ch_t_rw_data_o),
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.douta_o (),
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.doutb_o (ch_t_rw_data_internal)
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.clkb_i (vga_clk_i),
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.addra_i (char_tiff_addr_128bit),
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.addrb_i (ch_t_addr_internal),
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.wea_i (char_tiff_wea),
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.dina_i (char_tiff_wdata_128bit),
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.douta_o (char_tiff_rdata_128bit),
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.doutb_o (ch_t_data_internal)
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);
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logic [CH_T_DATA_WIDTH-1:0] ch_t_data_internal;
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assign ch_t_data_internal = ch_t_addr_internal[CH_T_ADDR_WIDTH] ? ch_t_rw_data_internal
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: ch_t_ro_data_internal;
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logic [7:0] col_map_data_internal;
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logic [7:0] col_map_data_internal_delayed;
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logic [3:0][7:0] col_map_data_internal_word;
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assign col_map_data_internal = col_map_data_internal_word[ch_map_addr_internal[1:0]];
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assign col_map_data_internal = col_map_data_internal_word[ch_map_byte_select_delayed];
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delay #(
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.DATA_WIDTH (8),
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.DELAY_BY (1)
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) col_map_data_delay (
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.clk_i (clk100m_i),
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.clk_i (vga_clk_i),
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.arstn_i (arstn_i),
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.data_i (col_map_data_internal),
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.data_o (col_map_data_internal_delayed)
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@@ -240,7 +264,7 @@ module vgachargen
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.ADDR_WIDTH (10)
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) col_map (
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.clka_i (clk_i),
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.clkb_i (clk100m_i),
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.clkb_i (vga_clk_i),
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.addra_i (col_map_addr_i),
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.addrb_i (ch_map_addr_internal[$left(ch_map_addr_internal):2]),
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.wea_i (col_map_be_gated),
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@@ -277,7 +301,7 @@ module vgachargen
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assign vga_vs_next = vga_vs_delayed;
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assign vga_hs_next = vga_hs_delayed;
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always_ff @(posedge clk100m_i or negedge arstn_i) begin
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always_ff @(posedge vga_clk_i or negedge arstn_i) begin
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if (!arstn_i) begin
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vga_r_ff <= '0;
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vga_g_ff <= '0;
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@@ -309,7 +333,8 @@ module clk_divider # (
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input logic arstn_i,
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output logic strb_o
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);
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localparam int unsigned COUNTER_WIDTH = (DIVISOR > 1) ? $clog2(DIVISOR) : 1;
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localparam int unsigned COUNTER_WIDTH = $clog2(DIVISOR);
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logic [COUNTER_WIDTH-1:0] counter_next;
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logic [COUNTER_WIDTH-1:0] counter_ff;
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@@ -394,28 +419,6 @@ module index_generator
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endmodule
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module single_port_ro_bram #(
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parameter INIT_FILE_NAME = "",
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parameter INIT_FILE_IS_BIN = 0,
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parameter int unsigned DATA_WIDTH = 2,
|
||||
parameter int unsigned ADDR_WIDTH = 4,
|
||||
localparam int unsigned DEPTH_WORDS = 2 ** ADDR_WIDTH
|
||||
) (
|
||||
input logic clk_i,
|
||||
input logic [ADDR_WIDTH-1:0] addr_i,
|
||||
output logic [DATA_WIDTH-1:0] dout_o
|
||||
);
|
||||
logic [DATA_WIDTH-1:0] mem[DEPTH_WORDS];
|
||||
|
||||
if (INIT_FILE_IS_BIN) initial $readmemb(INIT_FILE_NAME, mem, 0, DEPTH_WORDS-1);
|
||||
else initial $readmemh(INIT_FILE_NAME, mem, 0, DEPTH_WORDS-1);
|
||||
|
||||
always_ff @(posedge clk_i) begin
|
||||
dout_o <= mem[addr_i];
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module timing_generator
|
||||
import vgachargen_pkg::*;
|
||||
(
|
||||
@@ -434,7 +437,6 @@ module timing_generator
|
||||
);
|
||||
|
||||
logic [VGA_MAX_H_WIDTH-1:0] hcount_ff;
|
||||
logic hcount_en;
|
||||
logic [VGA_MAX_H_WIDTH-1:0] hcount_next;
|
||||
|
||||
logic [VGA_MAX_V_WIDTH-1:0] vcount_ff;
|
||||
@@ -602,6 +604,7 @@ module vga_block
|
||||
);
|
||||
logic clk_divider_strb;
|
||||
|
||||
if (CLK_FACTOR_25M > 1) begin
|
||||
clk_divider # (
|
||||
.DIVISOR (CLK_FACTOR_25M)
|
||||
) clk_divider (
|
||||
@@ -609,6 +612,9 @@ module vga_block
|
||||
.arstn_i,
|
||||
.strb_o (clk_divider_strb)
|
||||
);
|
||||
end else begin
|
||||
assign clk_divider_strb = 1'b1;
|
||||
end
|
||||
|
||||
timing_generator timing_generator (
|
||||
.clk_i,
|
||||
|
||||
Reference in New Issue
Block a user