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Andrei Solodovnikov
291
Labs/06. Main memory/tb_data_mem.sv
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291
Labs/06. Main memory/tb_data_mem.sv
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/* -----------------------------------------------------------------------------
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* Project Name : Architectures of Processor Systems (APS) lab work
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* Organization : National Research University of Electronic Technology (MIET)
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* Department : Institute of Microdevices and Control Systems
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* Author(s) : Andrei Solodovnikov
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* Email(s) : hepoh@org.miet.ru
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See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
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* ------------------------------------------------------------------------------
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*/
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module tb_data_mem;
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// Входы
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import memory_pkg::DATA_MEM_SIZE_WORDS;
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import memory_pkg::DATA_MEM_SIZE_BYTES;
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logic clk_i;
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logic mem_req_i;
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logic write_enable_i;
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logic [3:0] byte_enable_i;
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logic [31:0] addr_i, addr;
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logic [31:0] write_data_i;
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assign addr = addr_i[2+:$clog2(DATA_MEM_SIZE_WORDS)];
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logic [31:0] read_data_o;
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logic ready_o;
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logic [31:0] last_read_data;
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logic [31:0] last_write_data;
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int err_cnt = 0;
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static bit simulation_finished;
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data_mem DUT (.*);
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task read_request(input logic [31:0] address, output logic [31:0] data);
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addr_i <= address;
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mem_req_i <= 1'b1;
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write_enable_i <= 1'b0;
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@(posedge clk_i);
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data = read_data_o;
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mem_req_i <= 1'b0;
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endtask
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task write_request( input logic [31:0] address, data, input [3:0] be);
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addr_i <= address;
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mem_req_i <= 1'b1;
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write_enable_i <= 1'b1;
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byte_enable_i <= be;
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write_data_i <= data;
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@(posedge clk_i);
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mem_req_i <= 1'b0;
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endtask
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task direct_read_test();
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logic [31:0] data;
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for(int i = 0; i < 128; i++) begin
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read_request(i, data);
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end
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if(DATA_MEM_SIZE_BYTES > 128) begin
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for(int i = 1; i <= 128; i++) begin
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read_request(DATA_MEM_SIZE_BYTES / 128 * i + i%4, data);
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end
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end
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endtask
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task direct_write_test();
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for(int i = 0; i < 128; i++) begin
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write_request(i, $urandom(), '1);
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end
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if(DATA_MEM_SIZE_BYTES > 128) begin
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for(int i = 1; i <= 128; i++) begin
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write_request(DATA_MEM_SIZE_BYTES / 128 * i + i%4, $urandom(), i%16);
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end
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end
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endtask
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task random_write_test();
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repeat(1000) begin
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write_request($urandom_range(0, DATA_MEM_SIZE_BYTES-1), $urandom(), $urandom_range(0, 15));
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end
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repeat(1000) begin
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write_request($urandom(), $urandom(), $urandom_range(0, 15));
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end
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endtask
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task random_read_test();
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logic [31:0] data;
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repeat(1000) begin
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read_request($urandom_range(0, DATA_MEM_SIZE_BYTES-1), data);
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end
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repeat(1000) begin
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read_request($urandom(), data);
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end
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endtask
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task incorrect_read_test();
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mem_req_i <= '0;
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write_enable_i <= '1;
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addr_i <= '0;
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@(posedge clk_i);
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write_enable_i <= '0;
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@(posedge clk_i);
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mem_req_i <= '1;
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@(posedge clk_i);
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endtask
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task incorrect_write_test();
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mem_req_i <= '0;
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write_enable_i <= '0;
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byte_enable_i <= '0;
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write_data_i <= '1;
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addr_i <= '0;
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@(posedge clk_i);
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mem_req_i <= '1;
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@(posedge clk_i);
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write_enable_i <= '1;
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@(posedge clk_i);
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byte_enable_i <= 4'b0010;
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@(posedge clk_i);
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endtask
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task random_test();
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repeat(1000) begin
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mem_req_i <= $urandom_range(1);
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write_enable_i <= $urandom_range(1);
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byte_enable_i <= $urandom_range(15);
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addr_i <= $urandom();
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write_data_i <= $urandom();
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@(posedge clk_i);
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end
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endtask
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initial begin
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$timeformat(-9, 3, "ns", 8);
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$display("Test has been started");
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DUT.ram[0] = '0;
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DUT.ram[DATA_MEM_SIZE_WORDS-1] = '0;
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DUT.ram[DATA_MEM_SIZE_WORDS] = '0;
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assert( DUT.ram[0] == 0) else begin
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$display("RAM has no element with index 0");
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$fatal;
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end
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assert( DUT.ram[DATA_MEM_SIZE_WORDS-1] == 0) else begin
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$display("RAM has no element with index %d", DATA_MEM_SIZE_WORDS-1);
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$fatal;
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end
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assert( DUT.ram[DATA_MEM_SIZE_WORDS] === 'x) else begin
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$display("RAM has element with index %d", DATA_MEM_SIZE_WORDS);
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$fatal;
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end
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assert( DUT.ram[0][0] == 0) else begin
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$display("RAM bit indexes started not from 0");
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$fatal;
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end
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assert( DUT.ram[0][31] == 0) else begin
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$display("RAM bit indexes ended not at 31");
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$fatal;
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end
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assert( DUT.ram[0][32] === 'x) else begin
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$display("RAM bit indexes ended not at 31");
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$fatal;
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end
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direct_write_test();
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direct_read_test();
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random_write_test();
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random_read_test();
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incorrect_read_test();
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incorrect_write_test();
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random_test();
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$display("\nTest has been finished\nNumber of errors: %d\n", err_cnt);
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simulation_finished = 1;
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$finish;
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end
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logic [31:0] ram_data;
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logic [31:0] addr_reg;
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always @(posedge clk_i) begin
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addr_reg <= addr;
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end
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assign ram_data = DUT.ram[addr_reg];
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initial begin
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clk_i = 0;
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forever #5 clk_i = ~clk_i;
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end
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ready_check: assert property (@(posedge clk_i) ready_o) else begin
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err_cnt++;
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$display("Error at %t. Value of ready is not equal 1.", $time);
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end
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correct_read_check: assert property (
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@(posedge clk_i)
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mem_req_i & !write_enable_i |=> read_data_o === ram_data
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) else begin
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err_cnt++;
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$display("Error at %t. Incorrect read_data_o: %08h instead of %08h", $time(), $sampled(read_data_o), $sampled(ram_data));
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end
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logic [31:0] write_data;
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always @(posedge clk_i) begin
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write_data <= write_data_i;
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end
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correct_write_check_0: assert property (
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@(posedge clk_i)
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mem_req_i & write_enable_i & byte_enable_i[0]|=> $past(write_data_i[7:0]) === ram_data[7:0]
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) else begin
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err_cnt++;
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$display("Error at %t. Incorrect value of ram[%01d][7:0]: %02h instead of %02h", $time(), $sampled(addr_reg), $sampled(ram_data[7:0]), $sampled(write_data_i[7:0]));
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end
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correct_write_check_1: assert property (
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@(posedge clk_i)
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mem_req_i & write_enable_i & byte_enable_i[1]|=> $past(write_data_i[15:8]) == ram_data[15:8]
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) else begin
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err_cnt++;
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$display("Error at %t. Incorrect value of ram[%01d][15:8]: %02h instead of %02h", $time(), $sampled(addr_reg), $sampled(ram_data[15:8]), $sampled(write_data_i[15:8]));
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end
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correct_write_check_2: assert property (
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@(posedge clk_i)
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mem_req_i & write_enable_i & byte_enable_i[2]|=> $past(write_data_i[23:16]) == ram_data[23:16]
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) else begin
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err_cnt++;
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$display("Error at %t. Incorrect value of ram[%d][23:16]: %02h instead of %02h", $time(), $sampled(addr_reg), $sampled(ram_data[23:16]), $sampled(write_data_i[23:16]));
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end
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correct_write_check_3: assert property (
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@(posedge clk_i)
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mem_req_i & write_enable_i & byte_enable_i[3]|=> $past(write_data_i[31:24]) == ram_data[31:24]
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) else begin
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err_cnt++;
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$display("Error at %t. Incorrect value of ram[%d][31:24]: %02h instead of %02h", $time(), $sampled(addr), $sampled(ram_data[31:24]), $sampled(write_data_i[31:24]));
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end
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incorrect_read_check: assert property (
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@(posedge clk_i)
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!mem_req_i | write_enable_i |=> $stable(read_data_o)
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) else begin
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err_cnt++;
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$display("Error at %t. read_data_o is unstable without read request", $time());
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end
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incorrect_write_check_0: assert property (
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@(posedge clk_i)
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(!mem_req_i | !write_enable_i | !byte_enable_i[0]) & $stable(addr) |=> $stable(ram_data[7:0])
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) else begin
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err_cnt++;
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$display("Error at %t. ram[%d][7:0] is unstable without write request", $time(), $sampled(addr_reg));
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end
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icorrect_write_check_1: assert property (
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@(posedge clk_i)
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(!mem_req_i | !write_enable_i | !byte_enable_i[1]) & $stable(addr) |=> $stable(ram_data[15:8])
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) else begin
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err_cnt++;
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$display("Error at %t. ram[%d][15:8] is unstable without write request", $time(), $sampled(addr_reg));
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end
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incorrect_write_check_2: assert property (
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@(posedge clk_i)
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(!mem_req_i | !write_enable_i | !byte_enable_i[2]) & $stable(addr) |=> $stable(ram_data[23:16])
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) else begin
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err_cnt++;
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$display("Error at %t. ram[%d][23:16] is unstable without write request", $time(), $sampled(addr_reg));
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end
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incorrect_write_check_3: assert property (
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@(posedge clk_i)
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(!mem_req_i | !write_enable_i | !byte_enable_i[3]) & $stable(addr) |=> $stable(ram_data[31:24])
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) else begin
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err_cnt++;
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$display("Error at %t. ram[%d][31:24] is unstable without write request", $time(), $sampled(addr_reg));
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end
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always @(posedge clk_i) begin
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if(simulation_finished) begin
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$finish;
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end
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end
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always @(posedge clk_i) begin
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if (err_cnt >= 10) begin
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$display("\nTest has been stopped after 10 errors"); $stop();
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end
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end
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endmodule
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