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Добавление кредитов в исходники

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This commit is contained in:
Andrei Solodovnikov
2024-02-21 11:48:18 +03:00
parent a01446eb43
commit 3dcb0b76f9
67 changed files with 686 additions and 251 deletions
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26
Labs/Made-up modules/lab_10.csr.sv
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@@ -1,3 +1,13 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module csr_controller (
input logic clk_i,
@@ -58,14 +68,14 @@ module csr_controller (
assign ljljlj = rs1_data_i;
always_comb begin
case (llafdh[2:0])
0: abvD3l <= ljljlj ^ rs1_data_i;
1: abvD3l <= ljljlj;
2: abvD3l <= ljljlj | ljiufdqwq;
3: abvD3l <= ~ljljlj & ljiufdqwq;
4: abvD3l <= ~rs1_data_i ^ ~ljljlj;
5: abvD3l <= ljiuasdf;
6: abvD3l <= ljiuasdf | ljiufdqwq;
7: abvD3l <= ~ljiuasdf & ljiufdqwq;
0: abvD3l = ljljlj ^ rs1_data_i;
1: abvD3l = ljljlj;
2: abvD3l = ljljlj | ljiufdqwq;
3: abvD3l = ~ljljlj & ljiufdqwq;
4: abvD3l = ~rs1_data_i ^ ~ljljlj;
5: abvD3l = ljiuasdf;
6: abvD3l = ljiuasdf | ljiufdqwq;
7: abvD3l = ~ljiuasdf & ljiufdqwq;
endcase
end