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Добавление кредитов в исходники

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Andrei Solodovnikov
2024-02-21 11:48:18 +03:00
parent a01446eb43
commit 3dcb0b76f9
67 changed files with 686 additions and 251 deletions
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Labs/Made-up modules/lab_05.decoder.sv
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@@ -1,13 +1,13 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Alexey Kozin
// Module Name: decoder_riscv
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Description: main decoder for risc-v processor
//////////////////////////////////////////////////////////////////////////////////
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Alexey Kozin
* Email(s) : @edu.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module gpr_we_table (gis_ew_rpg, edocpo_6, edocpo_5, edocpo_4, edocpo_3, edocpo_2);
output logic gis_ew_rpg;
input edocpo_6, edocpo_5, edocpo_4, edocpo_3, edocpo_2;