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Добавление кредитов в исходники
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@@ -1,3 +1,26 @@
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//////////////////////////////////////////////////////////////////////////////////
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// Company: Digilent Inc.
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// Engineer: Thomas Kappenman
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//
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// Create Date: 03/03/2015 09:33:36 PM
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// Design Name:
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// Module Name: PS2Receiver
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// Project Name: Nexys4DDR Keyboard Demo
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// Target Devices: Nexys4DDR
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// Tool Versions:
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// Description: PS2 Receiver module used to shift in keycodes from a keyboard plugged into the PS2 port
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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// Modified in 2023 by engineers of
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// National Research University of Electronic Technology
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// Nikita Bulavin and Andrei Solodovnikov
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//
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//////////////////////////////////////////////////////////////////////////////////
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module PS2Receiver(
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input logic clk_i,
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input logic rst_i,
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@@ -1,3 +1,13 @@
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/* -----------------------------------------------------------------------------
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* Project Name : Architectures of Processor Systems (APS) lab work
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* Organization : National Research University of Electronic Technology (MIET)
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* Department : Institute of Microdevices and Control Systems
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* Author(s) : Nikita Bulavin
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* Email(s) : nekkit6@edu.miet.ru
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See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
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* ------------------------------------------------------------------------------
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*/
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module hex_digits(
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input logic clk_i,
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input logic rst_i,
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@@ -8,6 +8,16 @@
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// CONDITIONS OF ANY KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations under the License.
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// This file has been taken from https://github.com/pulp-platform/apb_uart_sv
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// and modified by Andrei Solodovnikov in order to be used in
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// Architectures of Processor Systems (APS) lab work project
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// Changelog:
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// some of the input signals has been hardcoded to constant values
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// cfg_div_i input has been replaced by baudrate_i input signal.
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// The signal cfg_div_i is now controled by baudrate_i input, and this control
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// logic is work from assumption that clk_i is 10 MHz.
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module uart_rx (
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input logic clk_i,
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input logic rst_i,
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@@ -8,6 +8,16 @@
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// CONDITIONS OF ANY KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations under the License.
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// This file has been taken from https://github.com/pulp-platform/apb_uart_sv
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// and modified by Andrei Solodovnikov in order to be used in
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// Architectures of Processor Systems (APS) lab work project
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// Changelog:
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// some of the input signals has been hardcoded to constant values
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// cfg_div_i input has been replaced by baudrate_i input signal.
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// The signal cfg_div_i is now controled by baudrate_i input, and this control
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// logic is work from assumption that clk_i is 10 MHz.
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module uart_tx (
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input logic clk_i,
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input logic rst_i,
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@@ -1,3 +1,13 @@
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/* -----------------------------------------------------------------------------
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* Project Name : Architectures of Processor Systems (APS) lab work
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* Organization : National Research University of Electronic Technology (MIET)
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* Department : Institute of Microdevices and Control Systems
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* Author(s) : Alexander Kharlamov
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* Email(s) : sasha_xarlamov@org.miet.ru
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See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
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* ------------------------------------------------------------------------------
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*/
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module vgachargen
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import vgachargen_pkg::*;
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#(
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/* -----------------------------------------------------------------------------
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* Project Name : Architectures of Processor Systems (APS) lab work
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* Organization : National Research University of Electronic Technology (MIET)
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* Department : Institute of Microdevices and Control Systems
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* Author(s) : Alexander Kharlamov
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* Email(s) : sasha_xarlamov@org.miet.ru
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See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
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* ------------------------------------------------------------------------------
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*/
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package vgachargen_pkg;
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parameter int unsigned HD = 640; // Display area
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