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Добавление кредитов в исходники

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This commit is contained in:
Andrei Solodovnikov
2024-02-21 11:48:18 +03:00
parent a01446eb43
commit 3dcb0b76f9
67 changed files with 686 additions and 251 deletions
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12
Labs/10. Interrupt subsystem/csr_pkg.sv
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@@ -1,3 +1,13 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
package csr_pkg;
localparam CSR_RW = 3'b001;
@@ -6,7 +16,7 @@ package csr_pkg;
localparam CSR_RWI = 3'b101;
localparam CSR_RSI = 3'b110;
localparam CSR_RCI = 3'b111;
localparam MIE_ADDR = 12'h304;
localparam MTVEC_ADDR = 12'h305;
localparam MSCRATCH_ADDR = 12'h340;

18
Labs/10. Interrupt subsystem/tb_csr.sv
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@@ -1,13 +1,13 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Daniil Strelkov
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Daniil Strelkov
* Email(s) : @edu.miet.ru
// Module Name: tb_csr
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Description: tb for CSR controller
//
//////////////////////////////////////////////////////////////////////////////////
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module tb_csr();
logic clk_i;

19
Labs/10. Interrupt subsystem/tb_irq.sv
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@@ -1,14 +1,13 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Daniil Strelkov
// Module Name: tb_irq
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Description: tb for interrupt controller
//
//////////////////////////////////////////////////////////////////////////////////
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Daniil Strelkov
* Email(s) : @edu.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module tb_irq();
logic clk_i;
logic rst_i;