Добавление кредитов в исходники

Labs/08. Load-store unit/tb_lsu.sv

@@ -1,13 +1,13 @@
-//////////////////////////////////////////////////////////////////////////////////
-// Company: MIET
-// Engineer: Andrei Solodovnikov
+/* -----------------------------------------------------------------------------
+* Project Name   : Architectures of Processor Systems (APS) lab work
+* Organization   : National Research University of Electronic Technology (MIET)
+* Department     : Institute of Microdevices and Control Systems
+* Author(s)      : Andrei Solodovnikov
+* Email(s)       : hepoh@org.miet.ru
 
-// Module Name:    lsu_testbench
-// Project Name:   RISCV_practicum
-// Target Devices: Nexys A7-100T
-// Description: tb for Load&Store module
-//
-//////////////////////////////////////////////////////////////////////////////////
+See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
+* ------------------------------------------------------------------------------
+*/
 module tb_lsu();
 import riscv_pkg::*;
 logic        clk_i        ;