MPSU/APS
1
0
Fork 0
mirror of https://github.com/MPSU/APS.git synced 2025-09-16 01:30:10 +00:00
Code Issues Packages Projects Releases Wiki Activity

Добавление кредитов в исходники

Browse Source
This commit is contained in:
Andrei Solodovnikov
2024-02-21 11:48:18 +03:00
parent a01446eb43
commit 3dcb0b76f9
67 changed files with 686 additions and 251 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
Labs/06. Datapath/alu_opcodes_pkg.sv
View File

@@ -1,3 +1,13 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
package alu_opcodes_pkg;
localparam ALU_OP_WIDTH = 5;

18
Labs/06. Datapath/board files/nexys_riscv_unit.sv
View File

@@ -1,11 +1,21 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Nikita Bulavin
* Email(s) : nekkit6@edu.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module nexys_riscv_unit(
input CLK100,
input resetn,
input BTND,
output CA, CB, CC, CD, CE, CF, CG,
output CA, CB, CC, CD, CE, CF, CG,
output [7:0] AN
);
riscv_unit unit(
.clk_i(btn),
.rst_i(!resetn)
@@ -14,7 +24,7 @@ module nexys_riscv_unit(
wire [31:0] instr_addr;
wire [31:0] instr;
reg btn;
assign instr_addr = unit.core.instr_addr_o;
assign instr = unit.core.instr_i;
@@ -140,7 +150,7 @@ module nexys_riscv_unit(
endcase
end
end
end
endmodule

12
Labs/06. Datapath/csr_pkg.sv
View File

@@ -1,3 +1,13 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
package csr_pkg;
localparam CSR_RW = 3'b001;
@@ -6,7 +16,7 @@ package csr_pkg;
localparam CSR_RWI = 3'b101;
localparam CSR_RSI = 3'b110;
localparam CSR_RCI = 3'b111;
localparam MIE_ADDR = 12'h304;
localparam MTVEC_ADDR = 12'h305;
localparam MSCRATCH_ADDR = 12'h340;

10
Labs/06. Datapath/riscv_pkg.sv
View File

@@ -1,3 +1,13 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Andrei Solodovnikov
* Email(s) : hepoh@org.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
package riscv_pkg;
import alu_opcodes_pkg::*;

18
Labs/06. Datapath/tb_riscv_unit.sv
View File

@@ -1,13 +1,13 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Nikita Bulavin
// Module Name: tb_riscv_unit
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Description: tb for datapath
//////////////////////////////////////////////////////////////////////////////////
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Nikita Bulavin
* Email(s) : nekkit6@edu.miet.ru
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module tb_riscv_unit();
reg clk;