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Добавление комментариев в constraints

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Это позволяет понимать к какому модулю относится какой файл
constraints.
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Солодовников Андрей Павлович
2025-10-08 10:09:21 +03:00
parent c045536401
commit 3d535f765b
6 changed files with 12 additions and 6 deletions
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3
Labs/01. Adder/board files/nexys_a7_100t.xdc
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## This file is a general .xdc for the Nexys A7-100T ## This file is a .xdc for module fulladder32
## running on the Nexys A7-100T
## To use it in a project: ## To use it in a project:
## - uncomment the lines corresponding to used pins ## - uncomment the lines corresponding to used pins
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project

3
Labs/02. Arithmetic-logic unit/board files/nexys_a7_100t.xdc
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## This file is a general .xdc for the Nexys A7-100T ## This file is a .xdc for module alu
## running on the Nexys A7-100T
## To use it in a project: ## To use it in a project:
## - uncomment the lines corresponding to used pins ## - uncomment the lines corresponding to used pins
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project

3
Labs/03. Register file and memory/board files/nexys_a7_100t.xdc
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## This file is a general .xdc for the Nexys A7-100T ## This file is a .xdc for module register_file
## running on the Nexys A7-100T
## To use it in a project: ## To use it in a project:
## - uncomment the lines corresponding to used pins ## - uncomment the lines corresponding to used pins
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project

3
Labs/04. Primitive programmable device/board files/nexys_a7_100t.xdc
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## This file is a general .xdc for the Nexys A7-100T ## This file is a .xdc for module CYBERcobra
## running on the Nexys A7-100T
## To use it in a project: ## To use it in a project:
## - uncomment the lines corresponding to used pins ## - uncomment the lines corresponding to used pins
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project

3
Labs/07. Datapath/board files/nexys_a7_100t.xdc
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## This file is a general .xdc for the Nexys A7-100T ## This file is a .xdc for module processor_system (labs 7-11)
## running on the Nexys A7-100T
## To use it in a project: ## To use it in a project:
## - uncomment the lines corresponding to used pins ## - uncomment the lines corresponding to used pins
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project

3
Labs/13. Peripheral units/nexys_a7_100t.xdc
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@@ -1,4 +1,5 @@
## This file is a general .xdc for the Nexys A7-100T ## This file is a .xdc for module processor_system (lab 13)
## running on the Nexys A7-100T
## To use it in a project: ## To use it in a project:
## - uncomment the lines corresponding to used pins ## - uncomment the lines corresponding to used pins
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project