From 3d535f765bd1a9e8326a135c20bba2887fd443d2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=D0=A1=D0=BE=D0=BB=D0=BE=D0=B4=D0=BE=D0=B2=D0=BD=D0=B8?= =?UTF-8?q?=D0=BA=D0=BE=D0=B2=20=D0=90=D0=BD=D0=B4=D1=80=D0=B5=D0=B9=20?= =?UTF-8?q?=D0=9F=D0=B0=D0=B2=D0=BB=D0=BE=D0=B2=D0=B8=D1=87?= Date: Wed, 8 Oct 2025 10:09:21 +0300 Subject: [PATCH] =?UTF-8?q?=D0=94=D0=BE=D0=B1=D0=B0=D0=B2=D0=BB=D0=B5?= =?UTF-8?q?=D0=BD=D0=B8=D0=B5=20=D0=BA=D0=BE=D0=BC=D0=BC=D0=B5=D0=BD=D1=82?= =?UTF-8?q?=D0=B0=D1=80=D0=B8=D0=B5=D0=B2=20=D0=B2=20constraints?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Это позволяет понимать к какому модулю относится какой файл constraints. --- Labs/01. Adder/board files/nexys_a7_100t.xdc | 3 ++- Labs/02. Arithmetic-logic unit/board files/nexys_a7_100t.xdc | 3 ++- .../03. Register file and memory/board files/nexys_a7_100t.xdc | 3 ++- .../board files/nexys_a7_100t.xdc | 3 ++- Labs/07. Datapath/board files/nexys_a7_100t.xdc | 3 ++- Labs/13. Peripheral units/nexys_a7_100t.xdc | 3 ++- 6 files changed, 12 insertions(+), 6 deletions(-) diff --git a/Labs/01. Adder/board files/nexys_a7_100t.xdc b/Labs/01. Adder/board files/nexys_a7_100t.xdc index 3a443b5..c28f6c5 100644 --- a/Labs/01. Adder/board files/nexys_a7_100t.xdc +++ b/Labs/01. Adder/board files/nexys_a7_100t.xdc @@ -1,4 +1,5 @@ -## This file is a general .xdc for the Nexys A7-100T +## This file is a .xdc for module fulladder32 +## running on the Nexys A7-100T ## To use it in a project: ## - uncomment the lines corresponding to used pins ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project diff --git a/Labs/02. Arithmetic-logic unit/board files/nexys_a7_100t.xdc b/Labs/02. Arithmetic-logic unit/board files/nexys_a7_100t.xdc index d74cfc7..e892458 100644 --- a/Labs/02. Arithmetic-logic unit/board files/nexys_a7_100t.xdc +++ b/Labs/02. Arithmetic-logic unit/board files/nexys_a7_100t.xdc @@ -1,4 +1,5 @@ -## This file is a general .xdc for the Nexys A7-100T +## This file is a .xdc for module alu +## running on the Nexys A7-100T ## To use it in a project: ## - uncomment the lines corresponding to used pins ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project diff --git a/Labs/03. Register file and memory/board files/nexys_a7_100t.xdc b/Labs/03. Register file and memory/board files/nexys_a7_100t.xdc index 63b6e46..7f21046 100644 --- a/Labs/03. Register file and memory/board files/nexys_a7_100t.xdc +++ b/Labs/03. Register file and memory/board files/nexys_a7_100t.xdc @@ -1,4 +1,5 @@ -## This file is a general .xdc for the Nexys A7-100T +## This file is a .xdc for module register_file +## running on the Nexys A7-100T ## To use it in a project: ## - uncomment the lines corresponding to used pins ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project diff --git a/Labs/04. Primitive programmable device/board files/nexys_a7_100t.xdc b/Labs/04. Primitive programmable device/board files/nexys_a7_100t.xdc index 1b7a70b..bbfb8d0 100644 --- a/Labs/04. Primitive programmable device/board files/nexys_a7_100t.xdc +++ b/Labs/04. Primitive programmable device/board files/nexys_a7_100t.xdc @@ -1,4 +1,5 @@ -## This file is a general .xdc for the Nexys A7-100T +## This file is a .xdc for module CYBERcobra +## running on the Nexys A7-100T ## To use it in a project: ## - uncomment the lines corresponding to used pins ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project diff --git a/Labs/07. Datapath/board files/nexys_a7_100t.xdc b/Labs/07. Datapath/board files/nexys_a7_100t.xdc index dd198ae..6dd0b43 100644 --- a/Labs/07. Datapath/board files/nexys_a7_100t.xdc +++ b/Labs/07. Datapath/board files/nexys_a7_100t.xdc @@ -1,4 +1,5 @@ -## This file is a general .xdc for the Nexys A7-100T +## This file is a .xdc for module processor_system (labs 7-11) +## running on the Nexys A7-100T ## To use it in a project: ## - uncomment the lines corresponding to used pins ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project diff --git a/Labs/13. Peripheral units/nexys_a7_100t.xdc b/Labs/13. Peripheral units/nexys_a7_100t.xdc index d2c6994..402a534 100644 --- a/Labs/13. Peripheral units/nexys_a7_100t.xdc +++ b/Labs/13. Peripheral units/nexys_a7_100t.xdc @@ -1,4 +1,5 @@ -## This file is a general .xdc for the Nexys A7-100T +## This file is a .xdc for module processor_system (lab 13) +## running on the Nexys A7-100T ## To use it in a project: ## - uncomment the lines corresponding to used pins ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project