diff --git a/Labs/01. Adder/board files/nexys_a7_100t.xdc b/Labs/01. Adder/board files/nexys_a7_100t.xdc
index 3a443b5..c28f6c5 100644
--- a/Labs/01. Adder/board files/nexys_a7_100t.xdc	
+++ b/Labs/01. Adder/board files/nexys_a7_100t.xdc	
@@ -1,4 +1,5 @@
-## This file is a general .xdc for the Nexys A7-100T
+## This file is a .xdc for module fulladder32
+## running on the Nexys A7-100T
 ## To use it in a project:
 ## - uncomment the lines corresponding to used pins
 ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
diff --git a/Labs/02. Arithmetic-logic unit/board files/nexys_a7_100t.xdc b/Labs/02. Arithmetic-logic unit/board files/nexys_a7_100t.xdc
index d74cfc7..e892458 100644
--- a/Labs/02. Arithmetic-logic unit/board files/nexys_a7_100t.xdc	
+++ b/Labs/02. Arithmetic-logic unit/board files/nexys_a7_100t.xdc	
@@ -1,4 +1,5 @@
-## This file is a general .xdc for the Nexys A7-100T
+## This file is a .xdc for module alu
+## running on the Nexys A7-100T
 ## To use it in a project:
 ## - uncomment the lines corresponding to used pins
 ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
diff --git a/Labs/03. Register file and memory/board files/nexys_a7_100t.xdc b/Labs/03. Register file and memory/board files/nexys_a7_100t.xdc
index 63b6e46..7f21046 100644
--- a/Labs/03. Register file and memory/board files/nexys_a7_100t.xdc	
+++ b/Labs/03. Register file and memory/board files/nexys_a7_100t.xdc	
@@ -1,4 +1,5 @@
-## This file is a general .xdc for the Nexys A7-100T
+## This file is a .xdc for module register_file
+## running on the Nexys A7-100T
 ## To use it in a project:
 ## - uncomment the lines corresponding to used pins
 ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
diff --git a/Labs/04. Primitive programmable device/board files/nexys_a7_100t.xdc b/Labs/04. Primitive programmable device/board files/nexys_a7_100t.xdc
index 1b7a70b..bbfb8d0 100644
--- a/Labs/04. Primitive programmable device/board files/nexys_a7_100t.xdc	
+++ b/Labs/04. Primitive programmable device/board files/nexys_a7_100t.xdc	
@@ -1,4 +1,5 @@
-## This file is a general .xdc for the Nexys A7-100T
+## This file is a .xdc for module CYBERcobra
+## running on the Nexys A7-100T
 ## To use it in a project:
 ## - uncomment the lines corresponding to used pins
 ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
diff --git a/Labs/07. Datapath/board files/nexys_a7_100t.xdc b/Labs/07. Datapath/board files/nexys_a7_100t.xdc
index dd198ae..6dd0b43 100644
--- a/Labs/07. Datapath/board files/nexys_a7_100t.xdc	
+++ b/Labs/07. Datapath/board files/nexys_a7_100t.xdc	
@@ -1,4 +1,5 @@
-## This file is a general .xdc for the Nexys A7-100T
+## This file is a .xdc for module processor_system (labs 7-11)
+## running on the Nexys A7-100T
 ## To use it in a project:
 ## - uncomment the lines corresponding to used pins
 ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
diff --git a/Labs/13. Peripheral units/nexys_a7_100t.xdc b/Labs/13. Peripheral units/nexys_a7_100t.xdc
index d2c6994..402a534 100644
--- a/Labs/13. Peripheral units/nexys_a7_100t.xdc	
+++ b/Labs/13. Peripheral units/nexys_a7_100t.xdc	
@@ -1,4 +1,5 @@
-## This file is a general .xdc for the Nexys A7-100T
+## This file is a .xdc for module processor_system (lab 13)
+## running on the Nexys A7-100T
 ## To use it in a project:
 ## - uncomment the lines corresponding to used pins
 ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project