Перевод Verilog-кода на SystemVerilog

This commit is contained in:
Andrei Solodovnikov
2023-11-15 14:47:28 +03:00
parent 1b4f666e25
commit 1da4ed0173
11 changed files with 200 additions and 200 deletions

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@@ -101,7 +101,7 @@ endmodule
Запрещено использовать процедурное присваивание (присваивание в блоке `always` или `initial`) объектам, не являющимися регистрами. Скорее всего, вы пытались выполнить `b = a;` или `b <= a;` блоке `always`/`initial`, где `b` является проводом.
```Verilog
```SystemVerilog
module adder(input a, input b, output c);
always @(*) begin
c = a ^ b; // ошибка, процедурное присваивание

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@@ -1,6 +1,6 @@
module half_divider(
input [31:0] numerator,
output[31:0] quotient
input logic [31:0] numerator,
output logic [31:0] quotient
);
assign quotient = numerator << 1'b1;

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@@ -1,11 +1,11 @@
module max_min(
input [31:0] a,
input [31:0] b,
output reg[31:0] max,
output reg[ 3:0] min
input logic [31:0] a,
input logic [31:0] b,
output logic [31:0] max,
output logic [ 3:0] min
);
always @(*) begin
always_comb @(*) begin
if(a > b) begin
max = a;
min = b;

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@@ -1,8 +1,8 @@
module tb();
reg [31:0] a;
reg [31:0] b;
wire [31:0] res;
logic [31:0] a;
logic [31:0] b;
logic [31:0] res;
vector_abs dut(
.x(a),
@@ -31,8 +31,8 @@ initial begin : test
a = 0; b = 0;
#5;
checker(a,b,res);
a = 1; b = 1;
#5;
checker(a,b,res);
@@ -40,14 +40,14 @@ initial begin : test
a = 3; b = 4;
#5;
checker(a,b,res);
for(i = 0; i < 100; i=i+1) begin
a = $random()&32'hff; b = $random()&32'hff;
#5;
checker(a,b,res);
end
$display("Test has been finished with %d errors", err_count);
if(err_count == 0) begin
$display("SUCCESS!");

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@@ -1,12 +1,12 @@
module vector_abs(
input [31:0] x,
input [31:0] y,
output[31:0] abs
input logic [31:0] x,
input logic [31:0] y,
output logic [31:0] abs
);
wire [31:0] min;
wire [31:0] min_half;
logic [31:0] min;
logic [31:0] min_half;
max_min max_min_unit(
.a(x),