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Перевод Verilog-кода на SystemVerilog
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@@ -101,7 +101,7 @@ endmodule
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Запрещено использовать процедурное присваивание (присваивание в блоке `always` или `initial`) объектам, не являющимися регистрами. Скорее всего, вы пытались выполнить `b = a;` или `b <= a;` блоке `always`/`initial`, где `b` является проводом.
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```Verilog
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```SystemVerilog
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module adder(input a, input b, output c);
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always @(*) begin
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c = a ^ b; // ошибка, процедурное присваивание
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@@ -1,6 +1,6 @@
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module half_divider(
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input [31:0] numerator,
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output[31:0] quotient
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input logic [31:0] numerator,
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output logic [31:0] quotient
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);
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assign quotient = numerator << 1'b1;
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@@ -1,11 +1,11 @@
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module max_min(
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input [31:0] a,
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input [31:0] b,
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output reg[31:0] max,
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output reg[ 3:0] min
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input logic [31:0] a,
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input logic [31:0] b,
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output logic [31:0] max,
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output logic [ 3:0] min
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);
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always @(*) begin
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always_comb @(*) begin
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if(a > b) begin
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max = a;
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min = b;
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@@ -1,8 +1,8 @@
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module tb();
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reg [31:0] a;
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reg [31:0] b;
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wire [31:0] res;
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logic [31:0] a;
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logic [31:0] b;
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logic [31:0] res;
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vector_abs dut(
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.x(a),
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@@ -31,8 +31,8 @@ initial begin : test
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a = 0; b = 0;
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#5;
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checker(a,b,res);
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a = 1; b = 1;
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#5;
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checker(a,b,res);
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@@ -40,14 +40,14 @@ initial begin : test
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a = 3; b = 4;
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#5;
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checker(a,b,res);
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for(i = 0; i < 100; i=i+1) begin
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a = $random()&32'hff; b = $random()&32'hff;
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#5;
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checker(a,b,res);
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end
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$display("Test has been finished with %d errors", err_count);
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if(err_count == 0) begin
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$display("SUCCESS!");
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@@ -1,12 +1,12 @@
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module vector_abs(
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input [31:0] x,
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input [31:0] y,
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output[31:0] abs
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input logic [31:0] x,
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input logic [31:0] y,
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output logic [31:0] abs
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);
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wire [31:0] min;
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wire [31:0] min_half;
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logic [31:0] min;
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logic [31:0] min_half;
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max_min max_min_unit(
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.a(x),
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