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APS/Other/vector_abs/max_min.sv
2023-11-15 14:47:47 +03:00

19 lines
275 B
Systemverilog

module max_min(
input logic [31:0] a,
input logic [31:0] b,
output logic [31:0] max,
output logic [ 3:0] min
);
always_comb @(*) begin
if(a > b) begin
max = a;
min = b;
end
else begin
max = b;
min = b;
end
end
endmodule