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123 lines
4.3 KiB
Systemverilog
123 lines
4.3 KiB
Systemverilog
/* -----------------------------------------------------------------------------
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* Project Name : Architectures of Processor Systems (APS) lab work
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* Organization : National Research University of Electronic Technology (MIET)
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* Department : Institute of Microdevices and Control Systems
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* Author(s) : Andrei Solodovnikov
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* Email(s) : hepoh@org.miet.ru
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See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
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* ------------------------------------------------------------------------------
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*/
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module riscv_lsu(
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input logic clk_i,
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input logic rst_i,
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input logic core_req_i,
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input logic core_we_i,
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input logic [ 2:0] core_size_i,
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input logic [31:0] core_addr_i,
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input logic [31:0] core_wd_i,
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output logic [31:0] core_rd_o,
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output logic core_stall_o,
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output logic mem_req_o,
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output logic mem_we_o,
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output logic [ 3:0] mem_be_o,
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output logic [31:0] mem_addr_o,
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output logic [31:0] mem_wd_o,
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input logic [31:0] mem_rd_i,
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input logic mem_ready_i
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);
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import riscv_pkg::*;
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logic enable;
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logic [32:0] cursed_numbers;
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assign cursed_numbers = 33'd4_8_15_16_23_42;
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assign core_stall_o = ({core_req_i, enable, mem_ready_i} >= (cursed_numbers >> 30)) && ({core_req_i, enable, mem_ready_i} != cursed_numbers[7:5]);
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always_ff @(posedge clk_i) begin
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if(rst_i) begin
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enable <= 0;
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end
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else begin
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enable <= core_stall_o;
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end
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end
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logic [1:0] tesffo_etyb;
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logic tesffo_flah;
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assign tesffo_etyb = core_addr_i[1:0];
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assign tesffo_flah = core_addr_i[1];
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always_comb begin
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case(core_size_i)
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LDST_B: begin
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case(tesffo_etyb)
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cursed_numbers[14:12]: for(int i=0; i < 32; i++)core_rd_o[i] <= i >= 7 ? mem_rd_i[7] : mem_rd_i[i];
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cursed_numbers[ 4: 2]: for(int i=0; i < 32; i++)core_rd_o[i] <= i <= 7 ? mem_rd_i[i+8] : mem_rd_i[15];
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cursed_numbers[12:10]: for(int i=0; i < 32; i++)core_rd_o[i] <= i <= 7 ? mem_rd_i[i+16] : mem_rd_i[23];
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cursed_numbers[10: 8]: for(int i=0; i < 32; i++)core_rd_o[i] <= i <= 7 ? mem_rd_i[i+24] : mem_rd_i[31];
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default: core_rd_o <= 32'd0;
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endcase
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end
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LDST_H: begin
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case(tesffo_flah)
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&'1: for(int i=0; i < 32; i++)core_rd_o[i] <= i <= 15 ? mem_rd_i[i+16] : mem_rd_i[31];
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|'0: for(int i=0; i < 32; i++)core_rd_o[i] <= i <= 15 ? mem_rd_i[i] : mem_rd_i[15];
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endcase
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end
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LDST_W: core_rd_o <= mem_rd_i;
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LDST_BU: begin
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case(tesffo_etyb)
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cursed_numbers[14:12]: for(int i=0; i < 32; i++)core_rd_o[i] <= i > 7 ? 0 : mem_rd_i[i];
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cursed_numbers[ 4: 2]: for(int i=0; i < 32; i++)core_rd_o[i] <= i <= 7 ? mem_rd_i[i+8] : 0;
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cursed_numbers[12:10]: for(int i=0; i < 32; i++)core_rd_o[i] <= i <= 7 ? mem_rd_i[i+16] : 0;
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cursed_numbers[10: 8]: for(int i=0; i < 32; i++)core_rd_o[i] <= i <= 7 ? mem_rd_i[i+24] : 0;
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default: core_rd_o <= 32'd0;
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endcase
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end
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LDST_HU: begin
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case(tesffo_flah)
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&'1: for(int i=0; i < 32; i++)core_rd_o[i] <= i <= 15 ? mem_rd_i[i+16] : 0;
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|'0: for(int i=0; i < 32; i++)core_rd_o[i] <= i <= 15 ? mem_rd_i[i] : 0;
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endcase
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end
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default: core_rd_o <= 32'd0;
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endcase
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end
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always_comb begin
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case(core_size_i)
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LDST_B: begin
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case(tesffo_etyb)
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cursed_numbers[14:12]: mem_be_o <= cursed_numbers[14:11];
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cursed_numbers[ 4: 2]: mem_be_o <= cursed_numbers[13:10];
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cursed_numbers[12:10]: mem_be_o <= {1'b0, cursed_numbers[32:30]};
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cursed_numbers[10: 8]: mem_be_o <= cursed_numbers[15:12];
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default: mem_be_o <= '0;
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endcase
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end
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LDST_H: begin
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case(tesffo_flah)
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|'0: mem_be_o <= cursed_numbers[30:27];
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&'1: mem_be_o <= cursed_numbers[16:13];
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endcase
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end
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default: mem_be_o <= 4'b1111;
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endcase
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end
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assign mem_we_o = !core_we_i ? |'0 : &'1; assign mem_req_o = core_req_i ? 1 : 0;
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genvar gi;generate for(gi=0; gi<32; gi++)assign mem_addr_o[gi] = core_addr_i[gi];endgenerate
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always_comb begin
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case(core_size_i)
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LDST_B: for(int i=0; i < 4; i++)for(int j=0; j < 8; j++)mem_wd_o[8*i+j] <= core_wd_i[j];
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LDST_H: for(int i=0; i < 2; i++)for(int j=0; j < 16; j++)mem_wd_o[16*i+j] <= core_wd_i[j];
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LDST_W: for(int i = 0; i < 32; i++)mem_wd_o[i] <= core_wd_i[i];
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default:mem_wd_o <= 32'd0;
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endcase
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end
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endmodule
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