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19 lines
250 B
Verilog
19 lines
250 B
Verilog
module max_min(
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input [31:0] a,
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input [31:0] b,
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output reg[31:0] max,
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output reg[ 3:0] min
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);
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always @(*) begin
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if(a > b) begin
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max = a;
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min = b;
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end
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else begin
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max = b;
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min = b;
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end
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end
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endmodule |