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53 lines
1.2 KiB
Systemverilog
53 lines
1.2 KiB
Systemverilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company: MIET
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// Engineer: Nikita Bulavin
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//
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// Create Date:
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// Design Name:
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// Module Name: tb_cybercobra
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// Project Name: RISCV_practicum
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// Target Devices: Nexys A7-100T
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// Tool Versions:
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// Description: tb for CYBERcobra 3000 Pro 2.1
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module tb_CYBERcobra();
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CYBERcobra dut(
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.clk_i(clk),
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.rst_i(rstn),
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.sw_i (sw_i ),
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.out_o(OUT)
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);
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wire [31:0] OUT;
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reg clk;
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reg rstn;
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reg [15:0] sw_i;
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initial clk <= 0;
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always #5 clk = ~clk;
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initial begin
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$display( "\nStart test: \n\n==========================\nCLICK THE BUTTON 'Run All'\n==========================\n"); $stop();
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rstn = 1'b1;
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#10;
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rstn = 1'b0;
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sw_i = 16'b100001000; //значение, до которого считает счетчик
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//#260;
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//sw_i = 15'b0;
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#10000;
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$display("\n The test is over \n See the internal signals of the CYBERcobra on the waveform \n");
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$finish;
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end
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endmodule
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