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131 lines
4.1 KiB
Systemverilog
131 lines
4.1 KiB
Systemverilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company: MIET
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// Engineer: Nikita Bulavin
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//
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// Create Date:
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// Design Name:
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// Module Name: tb_data_mem
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// Project Name: RISCV_practicum
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// Target Devices: Nexys A7-100T
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// Tool Versions:
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// Description: tb for data memory
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module tb_data_mem();
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parameter ADDR_SIZE = 4096;
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parameter TIME_OPERATION = 50;
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logic CLK;
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logic REQ;
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logic WE;
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logic [31:0] A;
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logic [31:0] WD;
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logic [31:0] RD;
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data_mem DUT (
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.clk_i (CLK),
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.mem_req_i (REQ),
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.write_enable_i (WE ),
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.addr_i (A ),
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.write_data_i (WD),
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.read_data_o (RD)
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);
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logic [31:0] RDa;
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integer i, err_count = 0;
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assign A = i;
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parameter CLK_FREQ_MHz = 100;
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parameter CLK_SEMI_PERIOD= 1e3/CLK_FREQ_MHz/2;
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initial CLK <= 0;
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always #CLK_SEMI_PERIOD CLK = ~CLK;
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initial begin
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$timeformat(-9, 2, " ns", 3);
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$display( "\nStart test: \n\n==========================\nCLICK THE BUTTON 'Run All'\n==========================\n"); $stop();
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REQ = 1;
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WE = 0;
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i = 1; #10;
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if (RD !== 32'hx) begin
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$display("The data memory should not be initialized by the $readmemh function");
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err_count = err_count + 1;
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end
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for (i = 0; i < ADDR_SIZE; i = i + 4) begin
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@(posedge CLK);
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WE = 1;
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WD = $urandom;
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end
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for (i = 0; i < (ADDR_SIZE+1); i = i + 1) begin
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if (i != (ADDR_SIZE+1)) begin
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REQ = |($urandom %10);
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WE = 0;
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#TIME_OPERATION;
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RDa = RD;
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WD = $urandom;
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#TIME_OPERATION;
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WE = $urandom % 2;
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#TIME_OPERATION;
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if ((WE && REQ || !REQ) && RD !== 32'd4195425967) begin
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$display("When writing (write_enable_i = %h) read_data_o should be equal to fa11_1eaf, your data: %h_%h, time: %t", WE, RD[31:16],RD[15:0], $time);
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err_count = err_count + 1;
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end
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if ((!WE && REQ) && RD !== RDa) begin
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$display("When reading (write_enable_i = %h), the data %h is overwritten with data %h at address %h, time: %t", WE, RDa, RD, A, $time);
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err_count = err_count + 1;
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end
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end
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else begin
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REQ = 1;
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#TIME_OPERATION;
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if (RD !== 32'd3735928559) begin
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$display("When reading (write_enable_i = %h) at an address greater than 4095, it should return dead_beef yor data: %h_%h, time: %t", WE, RD[31:16],RD[15:0], $time);
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err_count = err_count + 1;
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end
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end
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#TIME_OPERATION;
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end
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#TIME_OPERATION;
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REQ = 1;
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WE = 1;
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#TIME_OPERATION;
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for (i = 0; i < 8; i = i + 4) begin
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WD = i? 32'hfecd_ba98: 32'h7654_3210;
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#TIME_OPERATION;
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end
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WE = 0;
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i = 2;
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#TIME_OPERATION;
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if (RD !== 32'hba98_7654) begin
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$display("data is being written to the cell incorrectly. RAM [0:7] must be 0x0123456789abcdef, time: %t", $time);
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err_count = err_count + 1;
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end
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@(posedge CLK)
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i = 0;
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@(negedge CLK);
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if (RD !== 32'hba98_7654) begin
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$display("reading from data memory must be synchronous, time: %t", $time);
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err_count = err_count + 1;
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end
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@(posedge CLK); #5;
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if (RD !== 32'h7654_3210) begin
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$display("synchronous data memory read error, time: %t", $time);
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err_count = err_count + 1;
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end
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$display("Number of errors: %d", err_count);
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if( !err_count ) $display("\ndata_mem SUCCESS!!!\n");
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$finish();
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end
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endmodule
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