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25 lines
1.5 KiB
Markdown
25 lines
1.5 KiB
Markdown
# Lab 9. Integration of the Load/Store Unit
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After implementing the load/store unit, it must be integrated into the processor system developed in Lab 7. Figure 1 shows a diagram illustrating the integration of components:
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_Figure 1. Connecting the LSU to the processor system._
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## Preparation Materials
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Before performing this lab, it is recommended to study the theoretical part of Lab #8.
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## Assignment
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Integrate the `lsu` module into the `processor_system` module.
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### Steps
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1. Integrate the `lsu` and `data_mem` modules into the `processor_system` module.
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1. Note that the `stall` signal logic must be removed from the `processor_system` module, since it has been moved inside the `lsu` module.
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2. After integration, verify the processor system using the [program](../07.%20Datapath/#Assignment) and verification environment from Lab 7.
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1. As with testing the CYBERcobra architecture processor, you will not be explicitly told whether the test passed. You need to manually check, cycle by cycle, that the processor correctly executes the instructions described in [_Listing 1_](../07.%20Datapath/#Assignment) of Lab 7 (see the procedure in Lab #4). To do this, first determine yourself what each instruction should do, and then verify that the processor does exactly that.
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2. Pay attention to how the instructions `sw`, `sh`, `sb`, `lw`, `lh`, `lb`, `lhu`, `lbu` are executed now.
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3. This lab does not require testing on FPGA.
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