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114 lines
2.5 KiB
Markdown
114 lines
2.5 KiB
Markdown
# Concatenation (Signal Merging)
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Concatenation allows assigning a multi-bit signal the "join" of several lower-width signals, or conversely, assigning a higher-width signal to a group of lower-width signals.
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The concatenation operator has the following form: `{sig1, sig2, ..., sign}`.
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Suppose we have the following set of signals:
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```Verilog
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logic a;
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logic b;
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logic [7:0] c;
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logic [1:0] d;
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logic [5:0] e;
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```
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And we want the wire `e` to receive the following signals:
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- the MSB of signal `e` receives signal `a`
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- the next bit receives signal `b`
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- the next 2 bits receive bits `[4:3]` of signal `c`
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- the 2 LSBs receive signal `d`
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This can be done using 4 continuous assignments:
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```Verilog
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logic a;
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logic b;
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logic [7:0] c;
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logic [1:0] d;
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logic [5:0] e;
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assign e[5] = a;
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assign e[4] = b;
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assign e[3:2] = c[4:3];
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assign e[1:0] = d;
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```
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or with a single assignment using concatenation:
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```Verilog
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logic a;
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logic b;
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logic [7:0] c;
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logic [1:0] d;
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logic [5:0] e;
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assign e = {a, b, c[4:3], d};
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```
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The reverse is also possible. Suppose we want to drive individual wires from separate bits of signal `e`:
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```Verilog
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logic a;
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logic b;
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logic [7:0] c;
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logic [1:0] d;
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logic [5:0] e;
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assign a = e[5];
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assign b = e[4];
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assign c[4:3] = e[3:2];
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assign d = e[1:0];
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```
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This operation can also be expressed as a single concatenation:
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```Verilog
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logic a;
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logic b;
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logic [7:0] c;
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logic [1:0] d;
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logic [5:0] e;
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assign {a, b, c[4:3], d} = e;
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```
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Additionally, concatenation can be used for **signal replication**. Replication is expressed as:
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```Verilog
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{a, {replication_count{signal_to_replicate}} ,b}
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```
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For example, to assign three copies of bits `[4:3]` of signal `c`, followed by signals `a` and `b`:
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```Verilog
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logic a;
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logic b;
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logic [7:0] c;
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logic [7:0] e;
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assign e = { {3{c[4:3]}}, a, b};
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```
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## Chapter Summary
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The concatenation operator can be used to group and replicate signals on either side of an assignment:
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- it can be used to assign a group of lower-width signals to a higher-width signal
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- it can be used to assign the corresponding bits of a higher-width signal to a group of lower-width signals.
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