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43 lines
1.3 KiB
Systemverilog
43 lines
1.3 KiB
Systemverilog
//////////////////////////////////////////////////////////////////////////////////
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// Company: MIET
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// Engineer: Nikita Bulavin
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// Module Name: tb_riscv_unit
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// Project Name: RISCV_practicum
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// Target Devices: Nexys A7-100T
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// Description: tb for datapath
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//////////////////////////////////////////////////////////////////////////////////
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module tb_riscv_unit();
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reg clk;
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reg rst;
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riscv_unit unit(
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.clk_i(clk),
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.rst_i(rst)
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);
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initial clk = 0;
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always #10 clk = ~clk;
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initial begin
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$display( "\nStart test: \n\n==========================\nCLICK THE BUTTON 'Run All'\n==========================\n"); $stop();
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rst = 1;
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#20;
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rst = 0;
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#800;
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$display("\n The test is over \n See the internal signals of the module on the waveform \n");
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$finish;
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end
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stall_seq: assert property (
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@(posedge unit.core.clk_i) disable iff ( unit.core.rst_i )
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unit.core.mem_req_o |-> (unit.core.stall_i || $past(unit.core.stall_i))
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)else $error("\nincorrect implementation of stall signal\n");
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stall_seq_fall: assert property (
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@(posedge unit.core.clk_i) disable iff ( unit.core.rst_i )
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(unit.core.stall_i) |=> !unit.core.stall_i
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)else $error("\nstall must fall exact one cycle after rising\n");
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endmodule
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