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21 lines
761 B
Systemverilog
21 lines
761 B
Systemverilog
/* -----------------------------------------------------------------------------
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* Project Name : Architectures of Processor Systems (APS) lab work
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* Organization : National Research University of Electronic Technology (MIET)
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* Department : Institute of Microdevices and Control Systems
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* Author(s) : Andrei Solodovnikov
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* Email(s) : hepoh@org.miet.ru
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See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
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* ------------------------------------------------------------------------------
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*/
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module fulladder32(
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input logic [31:0] a_i,
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input logic [31:0] b_i,
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input logic carry_i,
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output logic [31:0] sum_o,
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output logic carry_o
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);
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assign {carry_o, sum_o} = a_i + b_i + carry_i;
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endmodule |