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27 lines
1001 B
Systemverilog
27 lines
1001 B
Systemverilog
/* -----------------------------------------------------------------------------
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* Project Name : Architectures of Processor Systems (APS) lab work
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* Organization : National Research University of Electronic Technology (MIET)
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* Department : Institute of Microdevices and Control Systems
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* Author(s) : Andrei Solodovnikov
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* Email(s) : hepoh@org.miet.ru
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See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
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* ------------------------------------------------------------------------------
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*/
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package csr_pkg;
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localparam CSR_RW = 3'b001;
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localparam CSR_RS = 3'b010;
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localparam CSR_RC = 3'b011;
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localparam CSR_RWI = 3'b101;
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localparam CSR_RSI = 3'b110;
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localparam CSR_RCI = 3'b111;
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localparam MIE_ADDR = 12'h304;
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localparam MTVEC_ADDR = 12'h305;
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localparam MSCRATCH_ADDR = 12'h340;
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localparam MEPC_ADDR = 12'h341;
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localparam MCAUSE_ADDR = 12'h342;
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endpackage
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