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90 lines
2.8 KiB
Systemverilog
90 lines
2.8 KiB
Systemverilog
/* -----------------------------------------------------------------------------
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* Project Name : Architectures of Processor Systems (APS) lab work
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* Organization : National Research University of Electronic Technology (MIET)
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* Department : Institute of Microdevices and Control Systems
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* Author(s) : Andrei Solodovnikov
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* Email(s) : hepoh@org.miet.ru
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See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
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* ------------------------------------------------------------------------------
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*/
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package riscv_pkg;
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import alu_opcodes_pkg::*;
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import csr_pkg::*;
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// opcodes
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localparam LOAD_OPCODE = 5'b00_000;
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localparam MISC_MEM_OPCODE = 5'b00_011;
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localparam OP_IMM_OPCODE = 5'b00_100;
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localparam AUIPC_OPCODE = 5'b00_101;
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localparam STORE_OPCODE = 5'b01_000;
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localparam OP_OPCODE = 5'b01_100;
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localparam LUI_OPCODE = 5'b01_101;
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localparam BRANCH_OPCODE = 5'b11_000;
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localparam JALR_OPCODE = 5'b11_001;
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localparam JAL_OPCODE = 5'b11_011;
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localparam SYSTEM_OPCODE = 5'b11_100;
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// dmem type load store
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localparam LDST_B = 3'b000;
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localparam LDST_H = 3'b001;
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localparam LDST_W = 3'b010;
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localparam LDST_BU = 3'b100;
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localparam LDST_HU = 3'b101;
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// operand a selection
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localparam OP_A_RS1 = 2'b00;
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localparam OP_A_CURR_PC = 2'b01;
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localparam OP_A_ZERO = 2'b10;
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// operand b selection
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localparam OP_B_RS2 = 3'b000;
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localparam OP_B_IMM_I = 3'b001;
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localparam OP_B_IMM_U = 3'b010;
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localparam OP_B_IMM_S = 3'b011;
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localparam OP_B_INCR = 3'b100;
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// writeback source selection
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localparam WB_EX_RESULT = 2'd0;
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localparam WB_LSU_DATA = 2'd1;
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localparam WB_CSR_DATA = 2'd2;
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/*
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Hack that makes nested opcodes be
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visible with just one import of
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riscv_pkg
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*/
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export alu_opcodes_pkg::ALU_OP_WIDTH;
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export alu_opcodes_pkg::ALU_ADD;
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export alu_opcodes_pkg::ALU_SUB;
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export alu_opcodes_pkg::ALU_XOR;
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export alu_opcodes_pkg::ALU_OR;
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export alu_opcodes_pkg::ALU_AND;
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export alu_opcodes_pkg::ALU_SRA;
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export alu_opcodes_pkg::ALU_SRL;
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export alu_opcodes_pkg::ALU_SLL;
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export alu_opcodes_pkg::ALU_LTS;
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export alu_opcodes_pkg::ALU_LTU;
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export alu_opcodes_pkg::ALU_GES;
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export alu_opcodes_pkg::ALU_GEU;
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export alu_opcodes_pkg::ALU_EQ;
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export alu_opcodes_pkg::ALU_NE;
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export alu_opcodes_pkg::ALU_SLTS;
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export alu_opcodes_pkg::ALU_SLTU;
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export csr_pkg::CSR_RW;
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export csr_pkg::CSR_RS;
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export csr_pkg::CSR_RC;
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export csr_pkg::CSR_RWI;
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export csr_pkg::CSR_RSI;
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export csr_pkg::CSR_RCI;
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export csr_pkg::MIE_ADDR;
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export csr_pkg::MTVEC_ADDR;
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export csr_pkg::MSCRATCH_ADDR;
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export csr_pkg::MEPC_ADDR;
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export csr_pkg::MCAUSE_ADDR;
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endpackage |