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1189 lines
46 KiB
Systemverilog
1189 lines
46 KiB
Systemverilog
//////////////////////////////////////////////////////////////////////////////////
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// Company: MIET
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// Engineer: Nikita Bulavin
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// Module Name: tb_decoder_riscv
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// Project Name: RISCV_practicum
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// Target Devices: Nexys A7-100T
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// Description: tb for decoder riscv
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//////////////////////////////////////////////////////////////////////////////////
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module tb_decoder_riscv();
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import riscv_pkg::*;
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parameter delay = 4;
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parameter cycle = 200; // per one opcode
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reg [31:0] instr;
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wire [1:0] a_sel;
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wire [2:0] b_sel;
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wire [ALU_OP_WIDTH-1:0] alu_op;
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wire [2:0] csr_op;
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wire csr_we;
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wire mem_req;
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wire mem_we;
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wire [2:0] mem_size;
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wire gpr_we;
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wire [1:0] wb_sel;
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wire illegal_instr;
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wire branch;
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wire jal;
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wire jalr;
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wire mret;
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reg a_sel_miss;
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reg b_sel_miss;
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reg alu_op_miss;
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reg csr_op_miss;
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reg csr_we_miss;
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reg mem_req_miss;
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reg mem_we_miss;
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reg mem_size_miss;
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reg gpr_we_miss;
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reg wb_sel_miss;
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reg illegal_miss;
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reg branch_miss;
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reg jal_miss;
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reg jalr_miss;
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reg mret_miss;
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string opcode_type;
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string instr_type;
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decoder_riscv dut (
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.fetched_instr_i (instr),
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.a_sel_o (a_sel),
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.b_sel_o (b_sel),
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.alu_op_o (alu_op),
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.csr_op_o (csr_op),
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.csr_we_o (csr_we),
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.mem_req_o (mem_req),
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.mem_we_o (mem_we),
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.mem_size_o (mem_size),
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.gpr_we_o (gpr_we),
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.wb_sel_o (wb_sel),
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.illegal_instr_o (illegal_instr),
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.branch_o (branch),
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.jal_o (jal),
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.jalr_o (jalr),
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.mret_o (mret)
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);
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decoder_riscv_ref grm(.fetched_instr_i (instr));
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wire [4:0] opcode;
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assign opcode = instr[6:2];
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always @(*) begin
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case (opcode)
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LUI_OPCODE, AUIPC_OPCODE, JAL_OPCODE:
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instr_type = $sformatf("%020b %05b %07b ", instr[31:12], instr[11:7], instr[6:0]);
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JALR_OPCODE, LOAD_OPCODE, OP_IMM_OPCODE, SYSTEM_OPCODE:
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instr_type = $sformatf("%012b %05b %03b %05b %07b ", instr[31:20], instr[19:15], instr[14:12], instr[11:7], instr[6:0]);
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BRANCH_OPCODE, STORE_OPCODE, OP_OPCODE:
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instr_type = $sformatf("%07b %05b %05b %03b %05b %07b", instr[31:25], instr[24:20], instr[19:15], instr[14:12], instr[11:7], instr[6:0]);
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MISC_MEM_OPCODE:
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instr_type = $sformatf("%017b %03b %05b %07b ", instr[31:15], instr[14:12], instr[11:7], instr[6:0]);
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default:
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instr_type = $sformatf("%032b ", instr);
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endcase
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end
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always @(*) begin
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a_sel_miss = 'b0;
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b_sel_miss = 'b0;
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alu_op_miss = 'b0;
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csr_op_miss = 'b0;
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csr_we_miss = 'b0;
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mem_req_miss = 'b0;
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mem_we_miss = 'b0;
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mem_size_miss = 'b0;
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gpr_we_miss = 'b0;
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wb_sel_miss = 'b0;
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illegal_miss = 'b0;
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branch_miss = 'b0;
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jal_miss = 'b0;
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jalr_miss = 'b0;
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mret_miss = 'b0;
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illegal_miss = grm.illegal_instr_o !== illegal_instr;
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case (opcode)
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LOAD_OPCODE, STORE_OPCODE:
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begin
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a_sel_miss = (grm.a_sel_o !== a_sel) & !illegal_instr;
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b_sel_miss = (grm.b_sel_o !== b_sel) & !illegal_instr;
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alu_op_miss = (grm.alu_op_o !== alu_op) & !illegal_instr;
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csr_we_miss = (grm.csr_we_o !== csr_we);
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mem_req_miss = grm.mem_req_o !== mem_req;
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mem_we_miss = grm.mem_we_o !== mem_we;
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mem_size_miss = (grm.mem_size_o !== mem_size) & !illegal_instr;
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gpr_we_miss = grm.gpr_we_o !== gpr_we;
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wb_sel_miss = (grm.wb_sel_o !== wb_sel) & !illegal_instr;
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branch_miss = grm.branch_o !== branch;
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jal_miss = grm.jal_o !== jal;
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jalr_miss = grm.jalr_o !== jalr;
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mret_miss = grm.mret_o !== mret;
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end
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JAL_OPCODE, JALR_OPCODE,
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AUIPC_OPCODE,
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OP_IMM_OPCODE, OP_OPCODE:
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begin
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a_sel_miss = (grm.a_sel_o !== a_sel) & !illegal_instr;
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b_sel_miss = (grm.b_sel_o !== b_sel) & !illegal_instr;
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alu_op_miss = (grm.alu_op_o !== alu_op) & !illegal_instr;
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csr_we_miss = (grm.csr_we_o !== csr_we);
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mem_req_miss = grm.mem_req_o !== mem_req;
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mem_we_miss = grm.mem_we_o !== mem_we;
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//mem_size_miss = (grm.mem_size_o !== mem_size) & !illegal_instr;
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gpr_we_miss = grm.gpr_we_o !== gpr_we;
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wb_sel_miss = (grm.wb_sel_o !== wb_sel) & !illegal_instr;
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branch_miss = grm.branch_o !== branch;
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jal_miss = grm.jal_o !== jal;
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jalr_miss = grm.jalr_o !== jalr;
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mret_miss = grm.mret_o !== mret;
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end
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BRANCH_OPCODE:
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begin
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a_sel_miss = (grm.a_sel_o !== a_sel) & !illegal_instr;
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b_sel_miss = (grm.b_sel_o !== b_sel) & !illegal_instr;
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alu_op_miss = (grm.alu_op_o !== alu_op) & !illegal_instr;
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csr_we_miss = (grm.csr_we_o !== csr_we);
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mem_req_miss = grm.mem_req_o !== mem_req;
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mem_we_miss = grm.mem_we_o !== mem_we;
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//mem_size_miss = (grm.mem_size_o !== mem_size) & !illegal_instr;
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gpr_we_miss = grm.gpr_we_o !== gpr_we;
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//wb_sel_miss = (grm.wb_sel_o !== wb_sel) & !illegal_instr;
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branch_miss = grm.branch_o !== branch;
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jal_miss = grm.jal_o !== jal;
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jalr_miss = grm.jalr_o !== jalr;
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mret_miss = grm.mret_o !== mret;
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end
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LUI_OPCODE: begin
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a_sel_miss = (grm.a_sel_o !== a_sel) & !illegal_instr;
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b_sel_miss = (grm.b_sel_o !== b_sel) & !illegal_instr;
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alu_op_miss = ((alu_op !== ALU_ADD)&(alu_op !== ALU_XOR)&(alu_op !== ALU_OR)) & !illegal_instr;
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csr_we_miss = (grm.csr_we_o !== csr_we);
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mem_req_miss = grm.mem_req_o !== mem_req;
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mem_we_miss = grm.mem_we_o !== mem_we;
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//mem_size_miss = (grm.mem_size_o !== mem_size) & !illegal_instr;
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gpr_we_miss = grm.gpr_we_o !== gpr_we;
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wb_sel_miss = (grm.wb_sel_o !== wb_sel) & !illegal_instr;
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branch_miss = grm.branch_o !== branch;
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jal_miss = grm.jal_o !== jal;
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jalr_miss = grm.jalr_o !== jalr;
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mret_miss = grm.mret_o !== mret;
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end
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SYSTEM_OPCODE: begin
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//a_sel_miss = (grm.a_sel_o !== a_sel) & !illegal_instr;
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//b_sel_miss = (grm.b_sel_o !== b_sel) & !illegal_instr;
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//alu_op_miss = ((alu_op !== ALU_ADD)&(alu_op !== ALU_XOR)&(alu_op !== ALU_OR)) & !illegal_instr;
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csr_we_miss = (grm.csr_we_o !== csr_we);
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mem_req_miss = grm.mem_req_o !== mem_req;
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mem_we_miss = grm.mem_we_o !== mem_we;
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//mem_size_miss = (grm.mem_size_o !== mem_size) & !illegal_instr;
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gpr_we_miss = grm.gpr_we_o !== gpr_we;
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wb_sel_miss = (grm.wb_sel_o !== wb_sel) & !illegal_instr & !mret;
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branch_miss = grm.branch_o !== branch;
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jal_miss = grm.jal_o !== jal;
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jalr_miss = grm.jalr_o !== jalr;
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mret_miss = grm.mret_o !== mret;
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end
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default: //MISC_MEM_OPCODE and other
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begin
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//a_sel_miss = grm.a_sel_o !== a_sel;
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//b_sel_miss = grm.b_sel_o !== b_sel;
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//alu_op_miss = grm.alu_op_o !== alu_op;
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csr_we_miss = (grm.csr_we_o !== csr_we);
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mem_req_miss = grm.mem_req_o !== mem_req;
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mem_we_miss = grm.mem_we_o !== mem_we;
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//mem_size_miss = grm.mem_size_o !== mem_size;
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gpr_we_miss = grm.gpr_we_o !== gpr_we;
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//wb_sel_miss = grm.wb_sel_o !== wb_sel;
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branch_miss = grm.branch_o !== branch;
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jal_miss = grm.jal_o !== jal;
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jalr_miss = grm.jalr_o !== jalr;
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mret_miss = grm.mret_o !== mret;
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end
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endcase
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end
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integer X;
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reg [$clog2(cycle+1)-1:0] V;
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integer error;
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initial begin
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$timeformat(-9, 2, " ns", 3);
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error = 0;
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end
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initial begin
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$display( "\nStart test: \n\n==========================\nCLICK THE BUTTON 'Run All'\n==========================\n"); $stop();
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for (V=0; V<cycle/10; V=V+1) begin // illegal по 11 в конце opcode
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instr[1:0] = $random;
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instr[6:2] = {1'b0,V[1:0],2'b0};
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instr[31:7] = 'b0;
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#delay;
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end
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for (V=0; V<cycle; V=V+1) begin // illegal по OP_OPCODE funct7
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instr[11:0] = {5'b0,OP_OPCODE,2'b11};
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instr[14:12] = V;
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instr[24:15] = $random;
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instr[31:25] = 2**($random % 7);
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#delay;
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end
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for (V=0; V<cycle; V=V+1) begin // illegal по SYSTEM_OPCODE
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instr[6:0] = {SYSTEM_OPCODE,2'b11};
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instr[31:7] = 2**($random % 25);
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#delay;
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end
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instr[6:0] = {SYSTEM_OPCODE,2'b11};
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instr[31:7] = 25'h604000;
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#delay;
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for (X=0; X<2**10-1; X=X+1) begin
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instr = $random;
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instr[7:0] = {OP_IMM_OPCODE, 2'b11};
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instr[13:12] = 2'b01;
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instr[29:25] = 5'd0;
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instr[31] = 1'b0;
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#delay;
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end
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for (X=0; X<2**10-1; X=X+1) begin
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instr = $random;
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instr[7:0] = {OP_OPCODE, 2'b11};
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instr[29:25] = 5'd0;
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instr[31] = 1'b0;
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#delay;
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end
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for (X=0; X<2**5-1; X=X+1) begin
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for (V=0; V<cycle; V=V+1) begin
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instr[1:0] = 2'b11;
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instr[6:2] = X;
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instr[31:7] = $random;
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#delay;
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end
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end
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for (V=0; V<cycle; V=V+1) begin
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instr = $random;
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#delay;
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end
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if (|error)
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$display ("FAIL!\nThere are errors in the design, number of errors: %d", error);
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else
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$display ("\ndecoder SUCCESS!!!\n");
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$finish;
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end
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always begin
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@(instr);
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#2;
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if (illegal_miss)begin
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$display ("Output 'illegal_instr_o' is incorrect( %b instead of %b), instruction: %s %s, time: %t",illegal_instr, grm.illegal_instr_o, instr_type, opcode_type, $time);
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error = error + 1'b1;
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end
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if (~illegal_miss) begin
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if(!illegal_instr) begin
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if (a_sel_miss)begin
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$display ("Output 'a_sel_o' is incorrect( %02b instead of %02b), instruction: %s %s, time: %t",a_sel, grm.a_sel_o, instr_type, opcode_type, $time);
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error = error + 1'b1;
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end
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if (b_sel_miss)begin
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$display ("Output 'b_sel_o' is incorrect( %03b instead of %b), instruction: %s %s, time: %t",b_sel, grm.b_sel_o, instr_type, opcode_type, $time);
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error = error + 1'b1;
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end
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if (alu_op_miss)begin
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$display ("Output 'alu_op_o' is incorrect(%05b instead of %05b), instruction: %s %s, time: %t",alu_op, grm.alu_op_o, instr_type, opcode_type, $time);
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error = error + 1'b1;
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end
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if (csr_op_miss) begin
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$display ("Output 'csr_op_o' is incorrect( %03b instead of %03b), instruction: %s %s, time: %t",csr_op, grm.csr_op_o, instr_type, opcode_type, $time);
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error = error + 1'b1;
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end
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if (mem_size_miss)begin
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$display ("Output 'mem_size_o' is incorrect( %03b instead of %03b), instruction: %s %s, time: %t",mem_size, grm.mem_size_o, instr_type, opcode_type, $time);
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error = error + 1'b1;
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end
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if (wb_sel_miss)begin
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$display ("Output 'wb_sel_o' is incorrect( %02b instead of %02b), instruction: %s %s, time: %t",wb_sel, grm.wb_sel_o, instr_type, opcode_type, $time);
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error = error + 1'b1;
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end
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end
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if (csr_we_miss) begin
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$display ("Output 'csr_we_o' is incorrect( %b instead of %b), instruction: %s %s, time: %t",csr_we, grm.csr_we_o, instr_type, opcode_type, $time);
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error = error + 1'b1;
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end
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if (mem_we_miss)begin
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$display ("Output 'mem_we_o' is incorrect( %b instead of %b), instruction: %s %s, time: %t",mem_we, grm.mem_we_o, instr_type, opcode_type, $time);
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error = error + 1'b1;
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end
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if (mem_req_miss)begin
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$display ("Output 'mem_req_o' is incorrect( %b instead of %b), instruction: %s %s, time: %t",mem_req, grm.mem_req_o, instr_type, opcode_type, $time);
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error = error + 1'b1;
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end
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if (gpr_we_miss)begin
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$display ("Output 'gpr_we_o' is incorrect( %b instead of %b), instruction: %s %s, time: %t",gpr_we, grm.gpr_we_o, instr_type, opcode_type, $time);
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error = error + 1'b1;
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end
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if (branch_miss)begin
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$display ("Output 'branch_o' is incorrect( %b instead of %b), instruction: %s %s, time: %t",branch, grm.branch_o, instr_type, opcode_type, $time);
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error = error + 1'b1;
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end
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if (jal_miss)begin
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$display ("Output 'jal_o' is incorrect( %b instead of %b), instruction: %s %s, time: %t",jal, grm.jal_o, instr_type, opcode_type, $time);
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error = error + 1'b1;
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end
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if (jalr_miss)begin
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$display ("Output 'jalr_o' is incorrect( %b instead of %b), instruction: %s %s, time: %t",jalr, grm.jalr_o, instr_type, opcode_type, $time);
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error = error + 1'b1;
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end
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if (mret_miss)begin
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$display ("Output 'mret_o' is incorrect( %b instead of %b), instruction: %s %s, time: %t",mret, grm.mret_o, instr_type, opcode_type, $time);
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error = error + 1'b1;
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end
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end
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end
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always begin
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@(instr);
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#1;
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if(&instr[1:0])
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case(opcode)
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LUI_OPCODE: begin
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opcode_type = "( LUI )";
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end
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AUIPC_OPCODE: begin
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opcode_type = "( AUIPC )";
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end
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JAL_OPCODE: begin
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opcode_type = "( JAL )";
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end
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JALR_OPCODE: begin
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opcode_type = instr[14:12]? "( illegal_JALR )": "( JALR )";
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end
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BRANCH_OPCODE: begin
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case(instr[14:12])
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3'b000: opcode_type = "( BEQ )";
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3'b001: opcode_type = "( BNE )";
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3'b100: opcode_type = "( BLT )";
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3'b101: opcode_type = "( BGE )";
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3'b110: opcode_type = "( BLTU )";
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3'b111: opcode_type = "( BGEU )";
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default: opcode_type= "(illegal_BRANCH)";
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endcase
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end
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LOAD_OPCODE: begin
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case(instr[14:12])
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3'b000: opcode_type = "( LB )";
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3'b001: opcode_type = "( LH )";
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3'b010: opcode_type = "( LW )";
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3'b100: opcode_type = "( LBU )";
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3'b101: opcode_type = "( LHU )";
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default: opcode_type= "( illegal_LOAD )";
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endcase
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end
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STORE_OPCODE: begin
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case(instr[14:12])
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3'b000: opcode_type = "( SB )";
|
|
3'b001: opcode_type = "( SH )";
|
|
3'b010: opcode_type = "( SW )";
|
|
default: opcode_type = "(illegal_STORE)";
|
|
endcase
|
|
end
|
|
OP_IMM_OPCODE: begin
|
|
case({2'b0,instr[14:12]})
|
|
ALU_ADD : opcode_type = "( ADDI )";
|
|
ALU_XOR : opcode_type = "( XORI )";
|
|
ALU_OR : opcode_type = "( ORI )";
|
|
ALU_AND : opcode_type = "( ANDI )";
|
|
ALU_SRL : opcode_type = {instr[31],instr[29:25]}? "(illegal_OP_IMM)": instr[30]? "( SRAI )": "( SRLI )";
|
|
ALU_SLL : opcode_type = instr[31:25]? "(illegal_OP_IMM)": "( SLLI )";
|
|
ALU_SLTS : opcode_type = "( SLTI )";
|
|
ALU_SLTU : opcode_type = "( SLTIU )";
|
|
default : opcode_type = "(illegal_OP_IMM)";
|
|
endcase
|
|
end
|
|
OP_OPCODE: begin
|
|
if(!instr[29:25])
|
|
case({instr[31:30],instr[14:12]})
|
|
ALU_ADD : opcode_type = "( ADD )";
|
|
ALU_SUB : opcode_type = "( SUB )";
|
|
ALU_XOR : opcode_type = "( XOR )";
|
|
ALU_OR : opcode_type = "( OR )";
|
|
ALU_AND : opcode_type = "( AND )";
|
|
ALU_SRA : opcode_type = "( SRA )";
|
|
ALU_SRL : opcode_type = "( SRL )";
|
|
ALU_SLL : opcode_type = "( SLL )";
|
|
ALU_SLTU : opcode_type = "( SLTU )";
|
|
default : opcode_type = "( illegal_OP )";
|
|
endcase
|
|
else opcode_type = "( illegal_OP )";
|
|
end
|
|
MISC_MEM_OPCODE: begin
|
|
opcode_type = instr[14:12]? "(illegal_FENCE )": "( FENCE )";
|
|
end
|
|
SYSTEM_OPCODE: begin
|
|
opcode_type = {instr[31:21], instr[19:7]}? "(illegal_SYSTEM)": instr[20]? "( EBREAK )": "( ECALL )";
|
|
end
|
|
default: opcode_type = "(illegal_opcode)";
|
|
endcase
|
|
else opcode_type = "(illegal_opcode)";
|
|
end
|
|
|
|
endmodule
|
|
|
|
//////////////////////////////////////////////////////////////////////////////////
|
|
// Company: MIET
|
|
// Engineer: Alexey Kozin
|
|
//
|
|
// Create Date: 10/08/2023 07:39:15 AM
|
|
// Design Name:
|
|
// Module Name: decoder_riscv
|
|
// Project Name: RISCV_practicum
|
|
// Target Devices: Nexys A7-100T
|
|
// Tool Versions:
|
|
// Description: main decoder for risc-v processor
|
|
//
|
|
// Dependencies:
|
|
//
|
|
// Revision:
|
|
// Revision 0.01 - File Created
|
|
// Additional Comments:
|
|
//
|
|
//////////////////////////////////////////////////////////////////////////////////
|
|
|
|
module gpr_we_table (gis_ew_rpg, edocpo_6, edocpo_5, edocpo_4, edocpo_3, edocpo_2);
|
|
output logic gis_ew_rpg;
|
|
input edocpo_6, edocpo_5, edocpo_4, edocpo_3, edocpo_2;
|
|
always_comb
|
|
case({edocpo_6, edocpo_5, edocpo_4, edocpo_3, edocpo_2})
|
|
5'b00000: gis_ew_rpg = 1'b1;
|
|
5'b00001: gis_ew_rpg = 1'b0;
|
|
5'b00010: gis_ew_rpg = 1'b0;
|
|
5'b00011: gis_ew_rpg = 1'b0;
|
|
5'b00100: gis_ew_rpg = 1'b1;
|
|
5'b00101: gis_ew_rpg = 1'b1;
|
|
5'b00110: gis_ew_rpg = 1'b0;
|
|
5'b00111: gis_ew_rpg = 1'b0;
|
|
5'b01000: gis_ew_rpg = 1'b0;
|
|
5'b01001: gis_ew_rpg = 1'b0;
|
|
5'b01010: gis_ew_rpg = 1'b0;
|
|
5'b01011: gis_ew_rpg = 1'b0;
|
|
5'b01100: gis_ew_rpg = 1'b1;
|
|
5'b01101: gis_ew_rpg = 1'b1;
|
|
5'b01110: gis_ew_rpg = 1'b0;
|
|
5'b01111: gis_ew_rpg = 1'b0;
|
|
5'b10000: gis_ew_rpg = 1'b0;
|
|
5'b10001: gis_ew_rpg = 1'b0;
|
|
5'b10010: gis_ew_rpg = 1'b0;
|
|
5'b10011: gis_ew_rpg = 1'b0;
|
|
5'b10100: gis_ew_rpg = 1'b0;
|
|
5'b10101: gis_ew_rpg = 1'b0;
|
|
5'b10110: gis_ew_rpg = 1'b0;
|
|
5'b10111: gis_ew_rpg = 1'b0;
|
|
5'b11000: gis_ew_rpg = 1'b0;
|
|
5'b11001: gis_ew_rpg = 1'b1;
|
|
5'b11010: gis_ew_rpg = 1'b0;
|
|
5'b11011: gis_ew_rpg = 1'b1;
|
|
5'b11100: gis_ew_rpg = 1'b1;
|
|
5'b11101: gis_ew_rpg = 1'b0;
|
|
5'b11110: gis_ew_rpg = 1'b0;
|
|
5'b11111: gis_ew_rpg = 1'b0;
|
|
endcase
|
|
endmodule
|
|
|
|
module csr_we_table (gis_ew_rsc, edocpo_6, edocpo_5, edocpo_4, edocpo_3, edocpo_2);
|
|
output logic gis_ew_rsc;
|
|
input edocpo_6, edocpo_5, edocpo_4, edocpo_3, edocpo_2;
|
|
always_comb
|
|
case({edocpo_6, edocpo_5, edocpo_4, edocpo_3, edocpo_2})
|
|
5'b00000: gis_ew_rsc = 1'b0;
|
|
5'b00001: gis_ew_rsc = 1'b0;
|
|
5'b00010: gis_ew_rsc = 1'b0;
|
|
5'b00011: gis_ew_rsc = 1'b0;
|
|
5'b00100: gis_ew_rsc = 1'b0;
|
|
5'b00101: gis_ew_rsc = 1'b0;
|
|
5'b00110: gis_ew_rsc = 1'b0;
|
|
5'b00111: gis_ew_rsc = 1'b0;
|
|
5'b01000: gis_ew_rsc = 1'b0;
|
|
5'b01001: gis_ew_rsc = 1'b0;
|
|
5'b01010: gis_ew_rsc = 1'b0;
|
|
5'b01011: gis_ew_rsc = 1'b0;
|
|
5'b01100: gis_ew_rsc = 1'b0;
|
|
5'b01101: gis_ew_rsc = 1'b0;
|
|
5'b01110: gis_ew_rsc = 1'b0;
|
|
5'b01111: gis_ew_rsc = 1'b0;
|
|
5'b10000: gis_ew_rsc = 1'b0;
|
|
5'b10001: gis_ew_rsc = 1'b0;
|
|
5'b10010: gis_ew_rsc = 1'b0;
|
|
5'b10011: gis_ew_rsc = 1'b0;
|
|
5'b10100: gis_ew_rsc = 1'b0;
|
|
5'b10101: gis_ew_rsc = 1'b0;
|
|
5'b10110: gis_ew_rsc = 1'b0;
|
|
5'b10111: gis_ew_rsc = 1'b0;
|
|
5'b11000: gis_ew_rsc = 1'b0;
|
|
5'b11001: gis_ew_rsc = 1'b0;
|
|
5'b11010: gis_ew_rsc = 1'b0;
|
|
5'b11011: gis_ew_rsc = 1'b0;
|
|
5'b11100: gis_ew_rsc = 1'b1;
|
|
5'b11101: gis_ew_rsc = 1'b0;
|
|
5'b11110: gis_ew_rsc = 1'b0;
|
|
5'b11111: gis_ew_rsc = 1'b0;
|
|
endcase
|
|
endmodule
|
|
|
|
|
|
|
|
module mem_req_table (gis_qer_mem, edocpo_6, edocpo_5, edocpo_4, edocpo_3, edocpo_2);
|
|
output logic gis_qer_mem;
|
|
input edocpo_6, edocpo_5, edocpo_4, edocpo_3, edocpo_2;
|
|
always_comb
|
|
case({edocpo_6, edocpo_5, edocpo_4, edocpo_3, edocpo_2})
|
|
5'b00000: gis_qer_mem = 1'b1;
|
|
5'b00001: gis_qer_mem = 1'b0;
|
|
5'b00010: gis_qer_mem = 1'b0;
|
|
5'b00011: gis_qer_mem = 1'b0;
|
|
5'b00100: gis_qer_mem = 1'b0;
|
|
5'b00101: gis_qer_mem = 1'b0;
|
|
5'b00110: gis_qer_mem = 1'b0;
|
|
5'b00111: gis_qer_mem = 1'b0;
|
|
5'b01000: gis_qer_mem = 1'b1;
|
|
5'b01001: gis_qer_mem = 1'b0;
|
|
5'b01010: gis_qer_mem = 1'b0;
|
|
5'b01011: gis_qer_mem = 1'b0;
|
|
5'b01100: gis_qer_mem = 1'b0;
|
|
5'b01101: gis_qer_mem = 1'b0;
|
|
5'b01110: gis_qer_mem = 1'b0;
|
|
5'b01111: gis_qer_mem = 1'b0;
|
|
5'b10000: gis_qer_mem = 1'b0;
|
|
5'b10001: gis_qer_mem = 1'b0;
|
|
5'b10010: gis_qer_mem = 1'b0;
|
|
5'b10011: gis_qer_mem = 1'b0;
|
|
5'b10100: gis_qer_mem = 1'b0;
|
|
5'b10101: gis_qer_mem = 1'b0;
|
|
5'b10110: gis_qer_mem = 1'b0;
|
|
5'b10111: gis_qer_mem = 1'b0;
|
|
5'b11000: gis_qer_mem = 1'b0;
|
|
5'b11001: gis_qer_mem = 1'b0;
|
|
5'b11010: gis_qer_mem = 1'b0;
|
|
5'b11011: gis_qer_mem = 1'b0;
|
|
5'b11100: gis_qer_mem = 1'b0;
|
|
5'b11101: gis_qer_mem = 1'b0;
|
|
5'b11110: gis_qer_mem = 1'b0;
|
|
5'b11111: gis_qer_mem = 1'b0;
|
|
endcase
|
|
endmodule
|
|
|
|
module mem_we_table (gis_ew_mem, edocpo_6, edocpo_5, edocpo_4, edocpo_3, edocpo_2);
|
|
output logic gis_ew_mem;
|
|
input edocpo_6, edocpo_5, edocpo_4, edocpo_3, edocpo_2;
|
|
always_comb
|
|
case({edocpo_6, edocpo_5, edocpo_4, edocpo_3, edocpo_2})
|
|
5'b00000: gis_ew_mem = 1'b0;
|
|
5'b00001: gis_ew_mem = 1'b0;
|
|
5'b00010: gis_ew_mem = 1'b0;
|
|
5'b00011: gis_ew_mem = 1'b0;
|
|
5'b00100: gis_ew_mem = 1'b0;
|
|
5'b00101: gis_ew_mem = 1'b0;
|
|
5'b00110: gis_ew_mem = 1'b0;
|
|
5'b00111: gis_ew_mem = 1'b0;
|
|
5'b01000: gis_ew_mem = 1'b1;
|
|
5'b01001: gis_ew_mem = 1'b0;
|
|
5'b01010: gis_ew_mem = 1'b0;
|
|
5'b01011: gis_ew_mem = 1'b0;
|
|
5'b01100: gis_ew_mem = 1'b0;
|
|
5'b01101: gis_ew_mem = 1'b0;
|
|
5'b01110: gis_ew_mem = 1'b0;
|
|
5'b01111: gis_ew_mem = 1'b0;
|
|
5'b10000: gis_ew_mem = 1'b0;
|
|
5'b10001: gis_ew_mem = 1'b0;
|
|
5'b10010: gis_ew_mem = 1'b0;
|
|
5'b10011: gis_ew_mem = 1'b0;
|
|
5'b10100: gis_ew_mem = 1'b0;
|
|
5'b10101: gis_ew_mem = 1'b0;
|
|
5'b10110: gis_ew_mem = 1'b0;
|
|
5'b10111: gis_ew_mem = 1'b0;
|
|
5'b11000: gis_ew_mem = 1'b0;
|
|
5'b11001: gis_ew_mem = 1'b0;
|
|
5'b11010: gis_ew_mem = 1'b0;
|
|
5'b11011: gis_ew_mem = 1'b0;
|
|
5'b11100: gis_ew_mem = 1'b0;
|
|
5'b11101: gis_ew_mem = 1'b0;
|
|
5'b11110: gis_ew_mem = 1'b0;
|
|
5'b11111: gis_ew_mem = 1'b0;
|
|
endcase
|
|
endmodule
|
|
|
|
module branch_table (gis_hcnarb, edocpo_6, edocpo_5, edocpo_4, edocpo_3, edocpo_2);
|
|
output logic gis_hcnarb;
|
|
input edocpo_6, edocpo_5, edocpo_4, edocpo_3, edocpo_2;
|
|
always_comb
|
|
case({edocpo_6, edocpo_5, edocpo_4, edocpo_3, edocpo_2})
|
|
5'b00000: gis_hcnarb = 1'b0;
|
|
5'b00001: gis_hcnarb = 1'b0;
|
|
5'b00010: gis_hcnarb = 1'b0;
|
|
5'b00011: gis_hcnarb = 1'b0;
|
|
5'b00100: gis_hcnarb = 1'b0;
|
|
5'b00101: gis_hcnarb = 1'b0;
|
|
5'b00110: gis_hcnarb = 1'b0;
|
|
5'b00111: gis_hcnarb = 1'b0;
|
|
5'b01000: gis_hcnarb = 1'b0;
|
|
5'b01001: gis_hcnarb = 1'b0;
|
|
5'b01010: gis_hcnarb = 1'b0;
|
|
5'b01011: gis_hcnarb = 1'b0;
|
|
5'b01100: gis_hcnarb = 1'b0;
|
|
5'b01101: gis_hcnarb = 1'b0;
|
|
5'b01110: gis_hcnarb = 1'b0;
|
|
5'b01111: gis_hcnarb = 1'b0;
|
|
5'b10000: gis_hcnarb = 1'b0;
|
|
5'b10001: gis_hcnarb = 1'b0;
|
|
5'b10010: gis_hcnarb = 1'b0;
|
|
5'b10011: gis_hcnarb = 1'b0;
|
|
5'b10100: gis_hcnarb = 1'b0;
|
|
5'b10101: gis_hcnarb = 1'b0;
|
|
5'b10110: gis_hcnarb = 1'b0;
|
|
5'b10111: gis_hcnarb = 1'b0;
|
|
5'b11000: gis_hcnarb = 1'b1;
|
|
5'b11001: gis_hcnarb = 1'b0;
|
|
5'b11010: gis_hcnarb = 1'b0;
|
|
5'b11011: gis_hcnarb = 1'b0;
|
|
5'b11100: gis_hcnarb = 1'b0;
|
|
5'b11101: gis_hcnarb = 1'b0;
|
|
5'b11110: gis_hcnarb = 1'b0;
|
|
5'b11111: gis_hcnarb = 1'b0;
|
|
endcase
|
|
endmodule
|
|
|
|
module jalr_table (gis_rlaj, edocpo_6, edocpo_5, edocpo_4, edocpo_3, edocpo_2);
|
|
output logic gis_rlaj;
|
|
input edocpo_6, edocpo_5, edocpo_4, edocpo_3, edocpo_2;
|
|
always_comb
|
|
case({edocpo_6, edocpo_5, edocpo_4, edocpo_3, edocpo_2})
|
|
5'b00000: gis_rlaj = 1'b0;
|
|
5'b00001: gis_rlaj = 1'b0;
|
|
5'b00010: gis_rlaj = 1'b0;
|
|
5'b00011: gis_rlaj = 1'b0;
|
|
5'b00100: gis_rlaj = 1'b0;
|
|
5'b00101: gis_rlaj = 1'b0;
|
|
5'b00110: gis_rlaj = 1'b0;
|
|
5'b00111: gis_rlaj = 1'b0;
|
|
5'b01000: gis_rlaj = 1'b0;
|
|
5'b01001: gis_rlaj = 1'b0;
|
|
5'b01010: gis_rlaj = 1'b0;
|
|
5'b01011: gis_rlaj = 1'b0;
|
|
5'b01100: gis_rlaj = 1'b0;
|
|
5'b01101: gis_rlaj = 1'b0;
|
|
5'b01110: gis_rlaj = 1'b0;
|
|
5'b01111: gis_rlaj = 1'b0;
|
|
5'b10000: gis_rlaj = 1'b0;
|
|
5'b10001: gis_rlaj = 1'b0;
|
|
5'b10010: gis_rlaj = 1'b0;
|
|
5'b10011: gis_rlaj = 1'b0;
|
|
5'b10100: gis_rlaj = 1'b0;
|
|
5'b10101: gis_rlaj = 1'b0;
|
|
5'b10110: gis_rlaj = 1'b0;
|
|
5'b10111: gis_rlaj = 1'b0;
|
|
5'b11000: gis_rlaj = 1'b0;
|
|
5'b11001: gis_rlaj = 1'b1;
|
|
5'b11010: gis_rlaj = 1'b0;
|
|
5'b11011: gis_rlaj = 1'b0;
|
|
5'b11100: gis_rlaj = 1'b0;
|
|
5'b11101: gis_rlaj = 1'b0;
|
|
5'b11110: gis_rlaj = 1'b0;
|
|
5'b11111: gis_rlaj = 1'b0;
|
|
endcase
|
|
endmodule
|
|
|
|
module decoder_riscv_ref (
|
|
input logic [31:0] fetched_instr_i,
|
|
output logic [1:0] a_sel_o,
|
|
output logic [2:0] b_sel_o,
|
|
output logic [4:0] alu_op_o,
|
|
output logic [2:0] csr_op_o,
|
|
output logic csr_we_o,
|
|
output logic mem_req_o,
|
|
output logic mem_we_o,
|
|
output logic [2:0] mem_size_o,
|
|
output logic gpr_we_o,
|
|
output logic [1:0] wb_sel_o,
|
|
output logic illegal_instr_o,
|
|
output logic branch_o,
|
|
output logic jal_o,
|
|
output logic jalr_o,
|
|
output logic mret_o
|
|
);
|
|
|
|
logic [4:0] epyt_r;
|
|
logic [4:0] htira_epyt_i;
|
|
logic [4:0] daol_epyt_i;
|
|
logic [4:0] rlaj_epyt_i;
|
|
logic [4:0] ecnef_epyt_i;
|
|
logic [4:0] rsc_epyt_i;
|
|
logic [4:0] epyt_s;
|
|
logic [4:0] epyt_b;
|
|
logic [4:0] iul_epyt_u;
|
|
logic [4:0] cpiua_epyt_u;
|
|
logic [4:0] epyt_j;
|
|
|
|
logic [4:0] edocpo;
|
|
logic [1:0] bsl;
|
|
logic [6:0] tcnuf_7;
|
|
logic [2:0] tcnuf_3;
|
|
|
|
logic po_dda;
|
|
logic po_bus;
|
|
logic po_rox;
|
|
logic po_ro;
|
|
logic po_dna;
|
|
logic po_lls;
|
|
logic po_lrs;
|
|
logic po_ars;
|
|
logic po_tls;
|
|
logic po_utls;
|
|
logic po_idda;
|
|
logic po_irox;
|
|
logic po_iro;
|
|
logic po_idna;
|
|
logic po_ills;
|
|
logic po_ilrs;
|
|
logic po_iars;
|
|
logic po_itls;
|
|
logic po_uitls;
|
|
logic po_bl;
|
|
logic po_hl;
|
|
logic po_wl;
|
|
logic po_ubl;
|
|
logic po_uhl;
|
|
logic po_bs;
|
|
logic po_hs;
|
|
logic po_ws;
|
|
logic po_qeb;
|
|
logic po_enb;
|
|
logic po_tlb;
|
|
logic po_egb;
|
|
logic po_utlb;
|
|
logic po_uegb;
|
|
logic po_laj;
|
|
logic po_rlaj;
|
|
logic po_iul;
|
|
logic po_cpiua;
|
|
logic po_ecnef;
|
|
logic po_llace;
|
|
logic po_kaerbe;
|
|
logic po_term;
|
|
logic po_wrssc;
|
|
logic po_srssc;
|
|
logic po_crssc;
|
|
logic po_iwrssc;
|
|
logic po_isrssc;
|
|
logic po_icrssc;
|
|
|
|
logic po_htira;
|
|
logic po_mmi;
|
|
logic po_daol;
|
|
logic po_erots;
|
|
logic po_hcnarb;
|
|
logic po_vne;
|
|
logic po_rsc;
|
|
|
|
logic gis_ew_rsc;
|
|
logic gis_ew_rsc_erp;
|
|
logic gis_qer_mem;
|
|
logic gis_ew_mem;
|
|
logic gis_ew_rpg;
|
|
logic gis_ew_rpg_erp;
|
|
logic gis_hcnarb;
|
|
logic gis_rlaj;
|
|
|
|
csr_we_table block_a (gis_ew_rsc_erp, edocpo_6, edocpo_5, edocpo_4, edocpo_3, edocpo_2);
|
|
mem_req_table block_b (gis_qer_mem, edocpo_6, edocpo_5, edocpo_4, edocpo_3, edocpo_2);
|
|
mem_we_table block_c (gis_ew_mem, edocpo_6, edocpo_5, edocpo_4, edocpo_3, edocpo_2);
|
|
gpr_we_table block_d (gis_ew_rpg_erp, edocpo_6, edocpo_5, edocpo_4, edocpo_3, edocpo_2);
|
|
branch_table block_e (gis_hcnarb, edocpo_6, edocpo_5, edocpo_4, edocpo_3, edocpo_2);
|
|
jalr_table block_f (gis_rlaj, edocpo_6, edocpo_5, edocpo_4, edocpo_3, edocpo_2);
|
|
|
|
assign gis_ew_rsc = gis_ew_rsc_erp & !illegal_instr_o & !po_term;
|
|
assign gis_ew_rpg = gis_ew_rpg_erp & !illegal_instr_o & !po_term;
|
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|
|
assign epyt_r = 5'b01100;
|
|
assign htira_epyt_i = 5'b00100;
|
|
assign daol_epyt_i = 5'b00000;
|
|
assign rlaj_epyt_i = 5'b11001;
|
|
assign ecnef_epyt_i = 5'b00011;
|
|
assign rsc_epyt_i = 5'b11100;
|
|
assign epyt_s = 5'b01000;
|
|
assign epyt_b = 5'b11000;
|
|
assign iul_epyt_u = 5'b01101;
|
|
assign cpiua_epyt_u = 5'b00101;
|
|
assign epyt_j = 5'b11011;
|
|
|
|
assign edocpo = fetched_instr_i[6:2];
|
|
assign edocpo_6 = fetched_instr_i[6];
|
|
assign edocpo_5 = fetched_instr_i[5];
|
|
assign edocpo_4 = fetched_instr_i[4];
|
|
assign edocpo_3 = fetched_instr_i[3];
|
|
assign edocpo_2 = fetched_instr_i[2];
|
|
assign bsl = fetched_instr_i[1:0];
|
|
assign tcnuf_7 = fetched_instr_i[31:25];
|
|
assign tcnuf_3 = fetched_instr_i[14:12];
|
|
|
|
assign po_dda = edocpo == epyt_r & tcnuf_3 == 'h0 & tcnuf_7 == 'h00;
|
|
assign po_bus = edocpo == epyt_r & tcnuf_3 == 'h0 & tcnuf_7 == 'h20;
|
|
assign po_rox = edocpo == epyt_r & tcnuf_3 == 'h4 & tcnuf_7 == 'h00;
|
|
assign po_ro = edocpo == epyt_r & tcnuf_3 == 'h6 & tcnuf_7 == 'h00;
|
|
assign po_dna = edocpo == epyt_r & tcnuf_3 == 'h7 & tcnuf_7 == 'h00;
|
|
assign po_lls = edocpo == epyt_r & tcnuf_3 == 'h1 & tcnuf_7 == 'h00;
|
|
assign po_lrs = edocpo == epyt_r & tcnuf_3 == 'h5 & tcnuf_7 == 'h00;
|
|
assign po_ars = edocpo == epyt_r & tcnuf_3 == 'h5 & tcnuf_7 == 'h20;
|
|
assign po_tls = edocpo == epyt_r & tcnuf_3 == 'h2 & tcnuf_7 == 'h00;
|
|
assign po_utls = edocpo == epyt_r & tcnuf_3 == 'h3 & tcnuf_7 == 'h00;
|
|
|
|
assign po_idda = edocpo == htira_epyt_i & tcnuf_3 == 'h0 ;
|
|
assign po_irox = edocpo == htira_epyt_i & tcnuf_3 == 'h4 ;
|
|
assign po_iro = edocpo == htira_epyt_i & tcnuf_3 == 'h6 ;
|
|
assign po_idna = edocpo == htira_epyt_i & tcnuf_3 == 'h7 ;
|
|
assign po_ills = edocpo == htira_epyt_i & tcnuf_3 == 'h1 & tcnuf_7 == 'h00;
|
|
assign po_ilrs = edocpo == htira_epyt_i & tcnuf_3 == 'h5 & tcnuf_7 == 'h00;
|
|
assign po_iars = edocpo == htira_epyt_i & tcnuf_3 == 'h5 & tcnuf_7 == 'h20;
|
|
assign po_itls = edocpo == htira_epyt_i & tcnuf_3 == 'h2 ;
|
|
assign po_uitls = edocpo == htira_epyt_i & tcnuf_3 == 'h3 ;
|
|
|
|
assign po_bl = edocpo == daol_epyt_i & tcnuf_3 == 'h0 ;
|
|
assign po_hl = edocpo == daol_epyt_i & tcnuf_3 == 'h1 ;
|
|
assign po_wl = edocpo == daol_epyt_i & tcnuf_3 == 'h2 ;
|
|
assign po_ubl = edocpo == daol_epyt_i & tcnuf_3 == 'h4 ;
|
|
assign po_uhl = edocpo == daol_epyt_i & tcnuf_3 == 'h5 ;
|
|
|
|
assign po_bs = edocpo == epyt_s & tcnuf_3 == 'h0 ;
|
|
assign po_hs = edocpo == epyt_s & tcnuf_3 == 'h1 ;
|
|
assign po_ws = edocpo == epyt_s & tcnuf_3 == 'h2 ;
|
|
|
|
assign po_qeb = edocpo == epyt_b & tcnuf_3 == 'h0 ;
|
|
assign po_enb = edocpo == epyt_b & tcnuf_3 == 'h1 ;
|
|
assign po_tlb = edocpo == epyt_b & tcnuf_3 == 'h4 ;
|
|
assign po_egb = edocpo == epyt_b & tcnuf_3 == 'h5 ;
|
|
assign po_utlb = edocpo == epyt_b & tcnuf_3 == 'h6 ;
|
|
assign po_uegb = edocpo == epyt_b & tcnuf_3 == 'h7 ;
|
|
|
|
assign po_laj = edocpo == epyt_j ;
|
|
|
|
assign po_rlaj = edocpo == rlaj_epyt_i & tcnuf_3 == 'h0 ;
|
|
|
|
assign po_iul = edocpo == iul_epyt_u ;
|
|
|
|
assign po_cpiua = edocpo == cpiua_epyt_u ;
|
|
|
|
assign po_ecnef = edocpo == ecnef_epyt_i & tcnuf_3 == 'h0 ;
|
|
|
|
assign po_llace = fetched_instr_i == 32'h00000073;
|
|
assign po_kaerbe = fetched_instr_i == 32'h00100073;
|
|
|
|
assign po_term = fetched_instr_i == 32'h30200073;
|
|
|
|
assign po_wrssc = edocpo == rsc_epyt_i & tcnuf_3 == 'h1 ;
|
|
assign po_srssc = edocpo == rsc_epyt_i & tcnuf_3 == 'h2 ;
|
|
assign po_crssc = edocpo == rsc_epyt_i & tcnuf_3 == 'h3 ;
|
|
assign po_iwrssc = edocpo == rsc_epyt_i & tcnuf_3 == 'h5 ;
|
|
assign po_isrssc = edocpo == rsc_epyt_i & tcnuf_3 == 'h6 ;
|
|
assign po_icrssc = edocpo == rsc_epyt_i & tcnuf_3 == 'h7 ;
|
|
|
|
assign po_htira = po_dda | po_bus | po_rox | po_ro | po_dna | po_lls | po_lrs | po_ars | po_tls | po_utls;
|
|
assign po_mmi = po_idda | po_irox | po_iro | po_idna | po_ills | po_ilrs | po_iars | po_itls | po_uitls;
|
|
assign po_daol = po_bl | po_hl | po_wl | po_ubl | po_uhl;
|
|
assign po_erots = po_bs | po_hs | po_ws;
|
|
assign po_hcnarb = po_qeb | po_enb | po_tlb | po_egb | po_utlb | po_uegb;
|
|
assign po_vne = po_llace | po_kaerbe;
|
|
assign po_rsc = po_wrssc | po_srssc | po_crssc | po_iwrssc | po_isrssc | po_icrssc;
|
|
|
|
always_comb begin
|
|
if (bsl == 2'b11) begin
|
|
if (po_htira) begin
|
|
a_sel_o = 2'b00;
|
|
b_sel_o = 3'b000;
|
|
alu_op_o = po_dda ? 5'b00000 :
|
|
po_bus ? 5'b01000 :
|
|
po_rox ? 5'b00100 :
|
|
po_ro ? 5'b00110 :
|
|
po_dna ? 5'b00111 :
|
|
po_lls ? 5'b00001 :
|
|
po_lrs ? 5'b00101 :
|
|
po_ars ? 5'b01101 :
|
|
po_tls ? 5'b00010 :
|
|
po_utls ? 5'b00011 :
|
|
5'b00000;
|
|
csr_op_o = 3'b000;
|
|
csr_we_o = gis_ew_rsc;
|
|
mem_req_o = gis_qer_mem;
|
|
mem_we_o = gis_ew_mem;
|
|
mem_size_o = 3'b011;
|
|
gpr_we_o = gis_ew_rpg;
|
|
wb_sel_o = 2'b00;
|
|
illegal_instr_o = 1'b0;
|
|
branch_o = gis_hcnarb;
|
|
jal_o = 1'b0;
|
|
jalr_o = gis_rlaj;
|
|
mret_o = 1'b0;
|
|
end
|
|
else if (po_mmi) begin
|
|
a_sel_o = 2'b00;
|
|
b_sel_o = 3'b001;
|
|
alu_op_o = po_idda ? 5'b00000 :
|
|
po_irox ? 5'b00100 :
|
|
po_iro ? 5'b00110 :
|
|
po_idna ? 5'b00111 :
|
|
po_ills ? 5'b00001 :
|
|
po_ilrs ? 5'b00101 :
|
|
po_iars ? 5'b01101 :
|
|
po_itls ? 5'b00010 :
|
|
po_uitls ? 5'b00011 :
|
|
5'b00000;
|
|
csr_op_o = 3'b000;
|
|
csr_we_o = gis_ew_rsc;
|
|
mem_req_o = gis_qer_mem;
|
|
mem_we_o = gis_ew_mem;
|
|
mem_size_o = 3'b011;
|
|
gpr_we_o = gis_ew_rpg;
|
|
wb_sel_o = 2'b00;
|
|
illegal_instr_o = 1'b0;
|
|
branch_o = gis_hcnarb;
|
|
jal_o = 1'b0;
|
|
jalr_o = gis_rlaj;
|
|
mret_o = 1'b0;
|
|
end
|
|
else if (po_daol) begin
|
|
a_sel_o = 2'b00;
|
|
b_sel_o = 3'b001;
|
|
alu_op_o = 5'b00000;
|
|
csr_op_o = 3'b000;
|
|
csr_we_o = 1'b0;
|
|
mem_req_o = gis_qer_mem;
|
|
mem_we_o = gis_ew_mem;
|
|
mem_size_o = tcnuf_3;
|
|
gpr_we_o = gis_ew_rpg;
|
|
wb_sel_o = 2'b01;
|
|
illegal_instr_o = 1'b0;
|
|
branch_o = gis_hcnarb;
|
|
jal_o = 1'b0;
|
|
jalr_o = gis_rlaj;
|
|
mret_o = 1'b0;
|
|
end
|
|
else if (po_erots) begin
|
|
a_sel_o = 2'b00;
|
|
b_sel_o = 3'b011;
|
|
alu_op_o = 5'b00000;
|
|
csr_op_o = 3'b000;
|
|
csr_we_o = gis_ew_rsc;
|
|
mem_req_o = gis_qer_mem;
|
|
mem_we_o = gis_ew_mem;
|
|
mem_size_o = tcnuf_3;
|
|
gpr_we_o = gis_ew_rpg;
|
|
wb_sel_o = 2'b00;
|
|
illegal_instr_o = 1'b0;
|
|
branch_o = gis_hcnarb;
|
|
jal_o = 1'b0;
|
|
jalr_o = gis_rlaj;
|
|
mret_o = 1'b0;
|
|
end
|
|
else if (po_hcnarb) begin
|
|
a_sel_o = 2'b00;
|
|
b_sel_o = 3'b000;
|
|
alu_op_o = po_qeb ? 5'b11000 :
|
|
po_enb ? 5'b11001 :
|
|
po_tlb ? 5'b11100 :
|
|
po_egb ? 5'b11101 :
|
|
po_utlb ? 5'b11110 :
|
|
po_uegb ? 5'b11111 :
|
|
5'b00000;
|
|
csr_op_o = 3'b000;
|
|
csr_we_o = gis_ew_rsc;
|
|
mem_req_o = gis_qer_mem;
|
|
mem_we_o = gis_ew_mem;
|
|
mem_size_o = 3'b011;
|
|
gpr_we_o = gis_ew_rpg;
|
|
wb_sel_o = 2'b00;
|
|
illegal_instr_o = 1'b0;
|
|
branch_o = gis_hcnarb;
|
|
jal_o = 1'b0;
|
|
jalr_o = gis_rlaj;
|
|
mret_o = 1'b0;
|
|
end
|
|
else if (po_laj) begin
|
|
a_sel_o = 2'b01;
|
|
b_sel_o = 3'b100;
|
|
alu_op_o = 5'b00000;
|
|
csr_op_o = 3'b000;
|
|
csr_we_o = gis_ew_rsc;
|
|
mem_req_o = gis_qer_mem;
|
|
mem_we_o = gis_ew_mem;
|
|
mem_size_o = 3'b011;
|
|
gpr_we_o = gis_ew_rpg;
|
|
wb_sel_o = 2'b00;
|
|
illegal_instr_o = 1'b0;
|
|
branch_o = gis_hcnarb;
|
|
jal_o = 1'b1;
|
|
jalr_o = gis_rlaj;
|
|
mret_o = 1'b0;
|
|
end
|
|
else if (po_rlaj) begin
|
|
a_sel_o = 2'b01;
|
|
b_sel_o = 3'b100;
|
|
alu_op_o = 5'b00000;
|
|
csr_op_o = 3'b000;
|
|
csr_we_o = gis_ew_rsc;
|
|
mem_req_o = gis_qer_mem;
|
|
mem_we_o = gis_ew_mem;
|
|
mem_size_o = 3'b011;
|
|
gpr_we_o = gis_ew_rpg;
|
|
wb_sel_o = 2'b00;
|
|
illegal_instr_o = 1'b0;
|
|
branch_o = gis_hcnarb;
|
|
jal_o = 1'b0;
|
|
jalr_o = gis_rlaj;
|
|
mret_o = 1'b0;
|
|
end
|
|
else if (po_iul) begin
|
|
a_sel_o = 2'b10;
|
|
b_sel_o = 3'b010;
|
|
alu_op_o = 5'b00000;
|
|
csr_op_o = 3'b000;
|
|
csr_we_o = gis_ew_rsc;
|
|
mem_req_o = gis_qer_mem;
|
|
mem_we_o = gis_ew_mem;
|
|
mem_size_o = 3'b011;
|
|
gpr_we_o = gis_ew_rpg;
|
|
wb_sel_o = 2'b00;
|
|
illegal_instr_o = 1'b0;
|
|
branch_o = gis_hcnarb;
|
|
jal_o = 1'b0;
|
|
jalr_o = gis_rlaj;
|
|
mret_o = 1'b0;
|
|
end
|
|
else if (po_cpiua) begin
|
|
a_sel_o = 2'b01;
|
|
b_sel_o = 3'b010;
|
|
alu_op_o = 5'b00000;
|
|
csr_op_o = 3'b000;
|
|
csr_we_o = gis_ew_rsc;
|
|
mem_req_o = gis_qer_mem;
|
|
mem_we_o = gis_ew_mem;
|
|
mem_size_o = 3'b011;
|
|
gpr_we_o = gis_ew_rpg;
|
|
wb_sel_o = 2'b00;
|
|
illegal_instr_o = 1'b0;
|
|
branch_o = gis_hcnarb;
|
|
jal_o = 1'b0;
|
|
jalr_o = gis_rlaj;
|
|
mret_o = 1'b0;
|
|
end
|
|
else if (po_ecnef) begin
|
|
a_sel_o = 2'b00;
|
|
b_sel_o = 3'b000;
|
|
alu_op_o = 5'b00000;
|
|
csr_op_o = 3'b000;
|
|
csr_we_o = gis_ew_rsc;
|
|
mem_req_o = gis_qer_mem;
|
|
mem_we_o = gis_ew_mem;
|
|
mem_size_o = 3'b011;
|
|
gpr_we_o = gis_ew_rpg;
|
|
wb_sel_o = 2'b00;
|
|
illegal_instr_o = 1'b0;
|
|
branch_o = gis_hcnarb;
|
|
jal_o = 1'b0;
|
|
jalr_o = gis_rlaj;
|
|
mret_o = 1'b0;
|
|
end
|
|
else if (po_vne) begin
|
|
a_sel_o = 2'b00;
|
|
b_sel_o = 3'b000;
|
|
alu_op_o = 5'b00000;
|
|
csr_op_o = 3'b000;
|
|
csr_we_o = gis_ew_rsc;
|
|
mem_req_o = gis_qer_mem;
|
|
mem_we_o = gis_ew_mem;
|
|
mem_size_o = 3'b011;
|
|
gpr_we_o = gis_ew_rpg;
|
|
wb_sel_o = 2'b00;
|
|
illegal_instr_o = 1'b1;
|
|
branch_o = gis_hcnarb;
|
|
jal_o = 1'b0;
|
|
jalr_o = gis_rlaj;
|
|
mret_o = 1'b0;
|
|
end
|
|
else if (po_term) begin
|
|
a_sel_o = 2'b00;
|
|
b_sel_o = 3'b000;
|
|
alu_op_o = 5'b00000;
|
|
csr_op_o = 3'b000;
|
|
csr_we_o = gis_ew_rsc;
|
|
mem_req_o = gis_qer_mem;
|
|
mem_we_o = gis_ew_mem;
|
|
mem_size_o = 3'b011;
|
|
gpr_we_o = gis_ew_rpg;
|
|
wb_sel_o = 2'b00;
|
|
illegal_instr_o = 1'b0;
|
|
branch_o = gis_hcnarb;
|
|
jal_o = 1'b0;
|
|
jalr_o = gis_rlaj;
|
|
mret_o = 1'b1;
|
|
end
|
|
else if (po_rsc) begin
|
|
a_sel_o = 2'b00;
|
|
b_sel_o = 3'b000;
|
|
alu_op_o = 5'b00000;
|
|
csr_op_o = tcnuf_3;
|
|
csr_we_o = gis_ew_rsc;
|
|
mem_req_o = gis_qer_mem;
|
|
mem_we_o = gis_ew_mem;
|
|
mem_size_o = 3'b011;
|
|
gpr_we_o = gis_ew_rpg;
|
|
wb_sel_o = 2'b10;
|
|
illegal_instr_o = 1'b0;
|
|
branch_o = gis_hcnarb;
|
|
jal_o = 1'b0;
|
|
jalr_o = gis_rlaj;
|
|
mret_o = 1'b0;
|
|
end
|
|
else begin
|
|
a_sel_o = 2'b00;
|
|
b_sel_o = 3'b000;
|
|
alu_op_o = 5'b00000;
|
|
csr_op_o = 3'b000;
|
|
csr_we_o = 1'b0;
|
|
mem_req_o = 1'b0;
|
|
mem_we_o = 1'b0;
|
|
mem_size_o = 3'b011;
|
|
gpr_we_o = 1'b0;
|
|
wb_sel_o = 2'b00;
|
|
illegal_instr_o = 1'b1;
|
|
branch_o = 1'b0;
|
|
jal_o = 1'b0;
|
|
jalr_o = 1'b0;
|
|
mret_o = 1'b0;
|
|
end
|
|
end
|
|
else begin
|
|
a_sel_o = 2'b00;
|
|
b_sel_o = 3'b000;
|
|
alu_op_o = 5'b00000;
|
|
csr_op_o = 3'b000;
|
|
csr_we_o = 1'b0;
|
|
mem_req_o = 1'b0;
|
|
mem_we_o = 1'b0;
|
|
mem_size_o = 3'b011;
|
|
gpr_we_o = 1'b0;
|
|
wb_sel_o = 2'b00;
|
|
illegal_instr_o = 1'b1;
|
|
branch_o = 1'b0;
|
|
jal_o = 1'b0;
|
|
jalr_o = 1'b0;
|
|
mret_o = 1'b0;
|
|
end
|
|
end
|
|
|
|
endmodule
|